公开(公告)号：US11929287B2

公开(公告)日：2024-03-12

申请号：US17238376

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Kuan-Ting Pan ,  Jung-Hung Chang ,  Lo-Heng Chang ,  Chien Ning Yao

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/823468 ,  H01L29/42392 ,  H01L29/78696

Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.

公开(公告)号：US11869955B2

公开(公告)日：2024-01-09

申请号：US17370822

申请日：2021-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8234 ,  H01L29/51 ,  H01L21/28 ,  H01L21/3115 ,  H01L27/088

CPC classification number: H01L29/42392 ,  H01L21/28185 ,  H01L21/3115 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0665 ,  H01L29/513 ,  H01L29/78696

Abstract: A method for processing an integrated circuit includes forming I/O gate all around transistors and core gate all around transistors. The method performs a regrowth process on an interfacial dielectric layer of the I/O gate all around transistors by diffusing metal atoms into the interfacial dielectric layer of the I/O gate all around transistor. The regrowth process does not diffuse metal atoms into the interfacial gate dielectric layer of the core gate all around transistor.

公开(公告)号：US11837504B2

公开(公告)日：2023-12-05

申请号：US17195282

申请日：2021-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Shi Ning Ju ,  Kuan-Lun Cheng ,  Kuan-Ting Pan

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/7843 ,  H01L21/845 ,  H01L27/1211

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having self-aligned isolation structures. The present disclosure provides self-aligned isolation fins that can be formed by depositing dielectric material in openings formed in a spacing layer or by replacing portions of fins with dielectric material. The self-aligned isolation fins can be separated from each other by a critical dimension of the utilized photolithography process. The separation between self-aligned isolation fins or between the self-aligned isolation fins and active fins can be approximately equal to or larger than the separations of the active fins.

公开(公告)号：US20230387268A1

公开(公告)日：2023-11-30

申请号：US18447953

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Chuan You ,  Li-Yang Chuang ,  Chih-Hao Wang ,  Shi Ning Ju ,  Kuo-Cheng Chiang

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/0649

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and an isolation structure between the first and second vertical structures. The isolation structure can include a center region and footing regions formed on opposite sides of the center region. Each of the footing regions can be tapered towards the center region from a first end of the each footing region to a second end of the each footing region.

公开(公告)号：US20230387127A1

公开(公告)日：2023-11-30

申请号：US18366004

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: The present disclosure provides a semiconductor structure that includes a substrate having a frontside and a backside; an active region extruded from the substrate and surrounded by an isolation feature; a gate stack formed on the front side of the substrate and disposed on the active region; a first and a second source/drain (S/D) feature formed on the active region and interposed by the gate stack; a frontside contact feature disposed on a top surface of the first S/D feature; a backside contact feature disposed on and electrically connected to a bottom surface of the second S/D feature; and a semiconductor layer disposed on a bottom surface of the first S/D feature with a first thickness and a bottom surface of the gate stack with a second thickness being greater than the first thickness.

公开(公告)号：US20230387124A1

公开(公告)日：2023-11-30

申请号：US18361704

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Chih-Hao Wang ,  Shi Ning Ju ,  Jia-Chuan You ,  Kuo-Cheng Chiang

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/823431 ,  H01L21/823418 ,  H01L21/823481

Abstract: A method includes providing a structure having two fins extending from a substrate; an isolation structure isolating bottom portions of the fins; source/drain (S/D) features over each of the fins; a dielectric fin oriented lengthwise parallel to the fins and disposed between the two fins and over the isolation structure; a dummy gate stack over the isolation structure, the fins, and the dielectric fin; and one or more dielectric layers over sidewalls of the dummy gate stack. The method further includes removing the dummy gate stack to result in a gate trench within the one or more dielectric layers, wherein the dielectric fin is exposed in the gate trench; trimming the dielectric fin to reduce a width of the dielectric fin; and after the trimming, forming a high-k metal gate in the gate trench.

公开(公告)号：US11799019B2

公开(公告)日：2023-10-24

申请号：US17091767

申请日：2020-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Huan-Chieh Su ,  Jia-Chuan You ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Yi-Ruei Jhan ,  Li-Yang Chuang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/6681 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0669

Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.

公开(公告)号：US20230290689A1

公开(公告)日：2023-09-14

申请号：US18308146

申请日：2023-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L21/84 ,  H01L21/8234 ,  H01L27/12 ,  H01L27/088 ,  H01L27/06

CPC classification number: H01L21/845 ,  H01L21/823431 ,  H01L21/823412 ,  H01L27/1211 ,  H01L27/0886 ,  H01L27/1207 ,  H01L27/0623

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device with fin structures having different top surface crystal orientations and/or different materials. The present disclosure provides a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and with fin structures having different materials. The present disclosure provides a method to fabricate a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and different materials to achieve optimized electron transport and hole transport. The present disclosure also provides a diode structure and a bipolar junction transistor structure that includes SiGe in the fin structures.

公开(公告)号：US11699729B2

公开(公告)日：2023-07-11

申请号：US17712605

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi Ning Ju ,  Guan-Lin Chen ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. The methods described herein allow for complex shapes (e.g., “L-shaped”) to be etched into a multi-layered stack to form fins used in the formation of active regions of the GAA nanostructure transistor structures. In some embodiments, the active regions may be formed with a first channel width and a first source/drain region having a first width and a second channel width and a second source/drain region having a second width that is less than the first width.

公开(公告)号：US11676864B2

公开(公告)日：2023-06-13

申请号：US17005172

申请日：2020-08-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuan-Ting Pan ,  Kuo-Cheng Chiang ,  Shi-Ning Ju ,  Shang-Wen Chang ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/823425 ,  H01L21/823481 ,  H01L27/0886

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first fin, a second fin adjacent the first fin, and a third fin adjacent the second fin. The structure further includes a first source/drain epitaxial feature merged with a second source/drain epitaxial feature. The structure further includes a third source/drain epitaxial feature, and a first liner positioned at a first distance away from a first plane defined by a first sidewall of the first fin and a second distance away from a second plane defined by a second sidewall of the second fin. The first distance is substantially the same as the second distance, and the merged first and second source/drain epitaxial features is disposed over the first liner. The structure further includes a dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature.