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    LATERAL BIPOLAR JUNCTION TRANSISTORS WITH A BACK-GATE
    211.
    发明申请
    LATERAL BIPOLAR JUNCTION TRANSISTORS WITH A BACK-GATE 有权

    公开(公告)号：US20230112235A1

    公开(公告)日：2023-04-13

    申请号：US17692517

    申请日：2022-03-11

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Hong Yu ,  Shesh Mani Pandey

    IPC: H01L29/10 ,  H01L29/66 ,  H01L29/735

    Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a substrate having a well, a first terminal including a first raised semiconductor layer, a second terminal including a second raised semiconductor layer, and a base layer positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The base layer has an overlapping arrangement with the well. The structure further includes a dielectric layer positioned in a vertical direction between the first terminal and the substrate, the second terminal and the substrate, and the base layer and the substrate.

    BIPOLAR TRANSISTOR STRUCTURE ON SEMICONDUCTOR FIN AND METHODS TO FORM SAME
    212.
    发明申请
    BIPOLAR TRANSISTOR STRUCTURE ON SEMICONDUCTOR FIN AND METHODS TO FORM SAME 有权

    公开(公告)号：US20230098557A1

    公开(公告)日：2023-03-30

    申请号：US17578687

    申请日：2022-01-19

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Hong Yu ,  Alexander M. Derrickson ,  Judson R. Holt

    IPC: H01L29/735 ,  H01L29/417 ,  H01L29/08 ,  H01L29/66

    Abstract: Embodiments of the disclosure provide a bipolar transistor structure on a semiconductor fin. The semiconductor fin may be on a substrate and may have a first doping type, a length in a first direction, and a width in a second direction perpendicular to the first direction. The semiconductor fin includes a first portion and a second portion adjacent the first portion along the length of the semiconductor fin. The second portion is coupled to a base contact. A dopant concentration of the first portion is less than a dopant concentration of the second portion. An emitter/collector (E/C) material is adjacent the first portion along the width of the semiconductor fin. The E/C material has a second doping type opposite the first doping type. The E/C material is coupled to an E/C contact.

    Optical ring modulator with photonic crystal
    216.
    发明授权
    Optical ring modulator with photonic crystal 有权

    公开(公告)号：US11609475B2

    公开(公告)日：2023-03-21

    申请号：US17119042

    申请日：2020-12-11

    Applicant: GLOBALFOUNDRIES U.S. INC.

    Inventor： Michal Rakowski ,  Yusheng Bian ,  Won Suk Lee ,  Roderick A. Augur

    IPC: G02F1/225

    Abstract: Embodiments of the disclosure provide an optical ring modulator. The optical ring modulator includes waveguide with a first semiconductor material of a first doping type, and a second semiconductor material having a second doping type adjacent the first semiconductor material. A P-N junction is between the first semiconductor material and the second semiconductor material. A plurality of photonic crystal layers, each embedded within the first semiconductor material or the second semiconductor material, has an upper surface that is substantially coplanar with an upper surface of the waveguide structure.

    DEVICE FOR ELECTROSTATIC DISCHARGE PROTECTION
    217.
    发明申请
    DEVICE FOR ELECTROSTATIC DISCHARGE PROTECTION 有权

    公开(公告)号：US20230085420A1

    公开(公告)日：2023-03-16

    申请号：US17471190

    申请日：2021-09-10

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Prantik MAHAJAN ,  Aloysius Priartanto HERLAMBANG ,  Kyong Jin HWANG ,  Robert John GAUTHIER, JR.

    IPC: H01L27/02 ,  H01L27/06 ,  H01L21/8224 ,  H01L21/762

    Abstract: A device includes a first region, a second region disposed on the first region, a third region and a fourth region abutting the third region disposed in the second region, a fifth region disposed in the third region and coupled to a collector disposed above, and a sixth region disposed in the fourth region and coupled to an emitter disposed above. A first isolation is disposed between the collector and the emitter. A seventh region is disposed in the fifth region and coupled to the collector is spaced apart from the first isolation. The first region, the third region, the fifth region, the collector and the emitter have a first conductivity type different from a second conductivity type that the second region, the fourth region, the sixth region and the seventh region have.

    LATERAL BIPOLAR TRANSISTOR STRUCTURE WITH INNER AND OUTER SPACERS AND METHODS TO FORM SAME
    218.
    发明申请
    LATERAL BIPOLAR TRANSISTOR STRUCTURE WITH INNER AND OUTER SPACERS AND METHODS TO FORM SAME 有权

    公开(公告)号：US20230083044A1

    公开(公告)日：2023-03-16

    申请号：US17457325

    申请日：2021-12-02

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Alexander M. Derrickson ,  John L. Lemon ,  Haiting Wang ,  Judson R. Holt

    IPC: H01L29/735 ,  H01L29/10 ,  H01L29/66

    Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with inner and outer spacers, and related methods. A lateral bipolar transistor structure may have an emitter/collector (E/C) layer over an insulator. The E/C layer has a first doping type. A first base layer is on the insulator and adjacent the E/C layer. The first base layer has a second doping type opposite the first doping type. A second base layer is on the first base layer and having the second doping type. A dopant concentration of the second base layer is greater than a dopant concentration of the first base layer. An inner spacer is on the E/C layer and adjacent the second base layer. An outer spacer is on the E/C layer and adjacent the inner spacer.

    RESISTIVE MEMORY ELEMENTS WITH AN EMBEDDED HEATING ELECTRODE
    219.
    发明申请
    RESISTIVE MEMORY ELEMENTS WITH AN EMBEDDED HEATING ELECTRODE 有权

    公开(公告)号：US20230071580A1

    公开(公告)日：2023-03-09

    申请号：US17467966

    申请日：2021-09-07

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Curtis Chun-I Hsieh ,  Juan Boon Tan ,  Calvin Lee

    IPC: H01L45/00

    Abstract: Structures for a resistive memory element and methods of forming a structure for a resistive memory element. A resistive memory element has a first electrode, a second electrode partially embedded in the first electrode, a third electrode, and a switching layer positioned between the first electrode and the third electrode. The second electrode includes a tip positioned in the first electrode adjacent to the switching layer and a sidewall that tapers to the tip.

    Floating gate memory cell and memory array structure
    220.
    发明授权
    Floating gate memory cell and memory array structure 有权

    公开(公告)号：US11600628B2

    公开(公告)日：2023-03-07

    申请号：US16743070

    申请日：2020-01-15

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Thomas Melde

    IPC: H01L27/11524 ,  H01L29/66 ,  H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H01L21/762 ,  H01L29/51

    Abstract: Embodiments of the disclosure provide a floating gate memory cell, including: a silicon-on-insulator (SOI) substrate, the SOI substrate including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, and a semiconductor layer formed on the buried oxide layer; a memory device, including: a control gate formed in the semiconductor layer of the SOI substrate; an insulating layer formed on the control gate; and a floating gate formed on the insulating layer; and a transistor device electrically connected to the memory device. The transistor device includes an active region formed in the semiconductor layer of the SOI substrate.

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