公开(公告)号：US11600628B2

公开(公告)日：2023-03-07

申请号：US16743070

申请日：2020-01-15

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Thomas Melde

IPC: H01L27/11524 ,  H01L29/66 ,  H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H01L21/762 ,  H01L29/51

Abstract: Embodiments of the disclosure provide a floating gate memory cell, including: a silicon-on-insulator (SOI) substrate, the SOI substrate including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, and a semiconductor layer formed on the buried oxide layer; a memory device, including: a control gate formed in the semiconductor layer of the SOI substrate; an insulating layer formed on the control gate; and a floating gate formed on the insulating layer; and a transistor device electrically connected to the memory device. The transistor device includes an active region formed in the semiconductor layer of the SOI substrate.

公开(公告)号：US20220223740A1

公开(公告)日：2022-07-14

申请号：US17147684

申请日：2021-01-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Thomas Melde ,  Stefan Dünkel ,  Ralf Richter

IPC: H01L29/788 ,  H01L27/11521 ,  H01L27/12 ,  H01L29/423

Abstract: A non-volatile memory (NVM) structure includes a first memory device including: a first inter-poly dielectric defined by an isolation layer over a first semiconductor layer over an insulator layer (SOI) stack over a bulk semiconductor substrate, a first tunneling insulator defined by the insulator layer, a first floating gate defined by the semiconductor layer of the SOI stack, and a first channel region defined in the bulk semiconductor substrate between a source region and a drain region. The memory device may also include a control gate over the SOI stack, an erase gate over a source region in the bulk substrate, and a bitline contact coupled to a drain region in the bulk substrate. The NVM structure may also include another memory device similar to the first memory device and sharing the source region.

公开(公告)号：US20230402091A1

公开(公告)日：2023-12-14

申请号：US17806792

申请日：2022-06-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Xiaoli Hu ,  Thomas Melde ,  Nicki N. Mika

IPC: G11C11/4099 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/56

CPC classification number: G11C11/4099 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/5635

Abstract: Structures herein include an array of non-volatile memory cells. The non-volatile memory cells include memory bit cells and at least one reference bit cell that is adjacent the memory bit cells. These structures also include at least one reference voltage regulator connected to the reference bit cell, and at least one sense amplifier connected to the memory bit cells and the reference voltage regulator.

公开(公告)号：US11825663B2

公开(公告)日：2023-11-21

申请号：US17403880

申请日：2021-08-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Johannes Müller ,  Thomas Melde ,  Stefan Dünkel ,  Ralf Richter

IPC: H10B53/30 ,  G11C11/22 ,  H10B53/10

CPC classification number: H10B53/30 ,  G11C11/221 ,  G11C11/2275 ,  H10B53/10

Abstract: A nonvolatile memory device is provided, the device comprising a ferroelectric memory capacitor arranged over a first active region contact of a first transistor and a gate contact of a second transistor, whereby the ferroelectric memory capacitor at least partially overlaps a gate of the first transistor.

公开(公告)号：US20250133735A1

公开(公告)日：2025-04-24

申请号：US18489672

申请日：2023-10-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicki Nico MIKA ,  Tom Herrmann ,  Thomas Melde

IPC: H10B41/30 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

Abstract: A non-volatile memory structure includes a semiconductor substrate and first and second memory devices on the semiconductor substrate. Each of the first and second memory devices includes a floating gate, a tunnelling insulator under the floating gate, an isolation layer over the floating gate, and at least one of a select gate and a control gate over the isolation layer. The non-volatile memory structure further includes an erase gate shared by the first and second memory devices, a source region under the erase gate, and a shallow trench isolation structure between the erase gate and the source region. The shallow trench isolation structure increases the number of write/erase cycles that can be performed by the non-volatile memory structure.

公开(公告)号：US20240332417A1

公开(公告)日：2024-10-03

申请号：US18127041

申请日：2023-03-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Thomas Melde ,  Ralf Richter ,  Stefan Dünkel

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66681

Abstract: Disclosed are embodiments of a semiconductor device and method of forming the device. The device includes a gate with first and second sections on a semiconductor layer. The first section includes first gate dielectric and gate conductor layers and an optional additional gate conductor layer on the first gate conductor layer. The second section includes second gate dielectric and gate conductor layers on the semiconductor layer and further extending onto the top of the first gate conductor layer. The second gate dielectric layer is thinner than the first gate dielectric layer. A gate sidewall spacer is on the first gate conductor layer positioned laterally to a sidewall of the second section (e.g., between the sidewall and the optional additional gate conductor layer). The first and second sections are either electrically connected for biasing with the gate bias voltage or electrically isolated for biasing with different gate bias voltages.

公开(公告)号：US12205633B2

公开(公告)日：2025-01-21

申请号：US17806792

申请日：2022-06-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Xiaoli Hu ,  Thomas Melde ,  Nicki N. Mika

IPC: G11C11/4099 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/56

Abstract: Structures herein include an array of non-volatile memory cells. The non-volatile memory cells include memory bit cells and at least one reference bit cell that is adjacent the memory bit cells. These structures also include at least one reference voltage regulator connected to the reference bit cell, and at least one sense amplifier connected to the memory bit cells and the reference voltage regulator.

公开(公告)号：US11631772B2

公开(公告)日：2023-04-18

申请号：US17147684

申请日：2021-01-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Thomas Melde ,  Stefan Dünkel ,  Ralf Richter

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/423 ,  H01L27/12

Abstract: A non-volatile memory (NVM) structure includes a first memory device including: a first inter-poly dielectric defined by an isolation layer over a first semiconductor layer over an insulator layer (SOI) stack over a bulk semiconductor substrate, a first tunneling insulator defined by the insulator layer, a first floating gate defined by the semiconductor layer of the SOI stack, and a first channel region defined in the bulk semiconductor substrate between a source region and a drain region. The memory device may also include a control gate over the SOI stack, an erase gate over a source region in the bulk substrate, and a bitline contact coupled to a drain region in the bulk substrate. The NVM structure may also include another memory device similar to the first memory device and sharing the source region.

公开(公告)号：US20210217758A1

公开(公告)日：2021-07-15

申请号：US16743070

申请日：2020-01-15

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Thomas Melde

IPC: H01L27/11524 ,  H01L29/66 ,  H01L21/762 ,  H01L21/28 ,  H01L29/51 ,  H01L29/423 ,  H01L29/788

Abstract: Embodiments of the disclosure provide a floating gate memory cell, including: a silicon-on-insulator (SOI) substrate, the SOI substrate including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, and a semiconductor layer formed on the buried oxide layer; a memory device, including: a control gate formed in the semiconductor layer of the SOI substrate; an insulating layer formed on the control gate; and a floating gate formed on the insulating layer; and a transistor device electrically connected to the memory device. The transistor device includes an active region formed in the semiconductor layer of the SOI substrate.