公开(公告)号：US11050500B2

公开(公告)日：2021-06-29

申请号：US16552919

申请日：2019-08-27

Applicant: Rambus Inc.

Inventor： Maksym Demchenko

IPC: H04J3/06 ,  H04L29/06 ,  H04L1/00 ,  H04L12/841

Abstract: In a general aspect, a network transmission interface can include, within an egress data path, a physical coding sublayer (PCS) operating in a constant bitrate domain for transmitting data frames on a network link; a timestamp unit configured to insert timestamps in payloads of the frames; a transmission media access control (MAC) unit located at a boundary between the constant bitrate domain and a variable bitrate domain, configured to receive the frames at a variable bitrate, encapsulate the frames, and provide the encapsulated frames at a constant bitrate; a MAC layer security unit located downstream from the timestamp unit, configured to sign and optionally encrypt the payloads and expand each frame with a security tag and an integrity check value (ICV). The timestamp unit and the MAC layer security unit (26b) can both operate in the constant bitrate domain.

公开(公告)号：US11049546B2

公开(公告)日：2021-06-29

申请号：US16865928

申请日：2020-05-04

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G06F1/3237 ,  G06F1/04 ,  G06F1/3234 ,  G06F1/08 ,  G11C11/408

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US20210193215A1

公开(公告)日：2021-06-24

申请号：US17135112

申请日：2020-12-28

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ming Li

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C5/02 ,  G11C5/04 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/48 ,  G11C11/406

Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

公开(公告)号：US11043258B2

公开(公告)日：2021-06-22

申请号：US16842368

申请日：2020-04-07

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

IPC: G11C7/00 ,  G11C11/4093 ,  H01L25/065 ,  H01L25/10 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G06F13/40 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  H01L25/18 ,  H01L23/00

Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

公开(公告)号：US20210183434A1

公开(公告)日：2021-06-17

申请号：US17115538

申请日：2020-12-08

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G11C11/406 ,  G06F13/16

Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

公开(公告)号：US11037652B2

公开(公告)日：2021-06-15

申请号：US16870759

申请日：2020-05-08

Applicant: Rambus Inc.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/48 ,  G11C29/04 ,  G11C11/401 ,  G11C29/12 ,  G11C11/408 ,  G11C29/02

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

公开(公告)号：US11036398B2

公开(公告)日：2021-06-15

申请号：US16535814

申请日：2019-08-08

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Michael Miller ,  Stephen Horn

IPC: G06F3/06 ,  G11C14/00 ,  G06F11/00 ,  G06F12/14 ,  G11C5/04 ,  G11C11/00 ,  G06F12/0802 ,  G06F13/16 ,  G11C7/10 ,  G06F11/14

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

公开(公告)号：US11029715B1

公开(公告)日：2021-06-08

申请号：US16853644

申请日：2020-04-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G05F1/567 ,  G05F1/56

Abstract: A voltage converter includes first and second inputs to receive a supply voltage and a reference voltage, respectively, from a power supply component, the supply voltage being higher than the reference voltage by a scaling factor of at least five. The voltage converter iteratively charges an internal filter capacitor to produce a converted voltage that follows the reference voltage by switchably coupling the first input to the filter capacitor while the converted voltage is less than the reference voltage to raise the converted voltage, and by switchably decoupling the first input from the filter capacitor while the converted voltage exceeds the reference voltage to enable the converted voltage to decay.

公开(公告)号：US11018907B2

公开(公告)日：2021-05-25

申请号：US16899513

申请日：2020-06-11

Applicant: Rambus Inc.

Inventor： Nanyan Wang

IPC: H03K7/02 ,  H03K9/02 ,  H04L25/06 ,  H04L5/00 ,  H04L25/49 ,  H04L27/00

Abstract: In a PAM-N receiver, sampler reference levels, DC offset and AFE gain may be jointly adapted to achieve optimal or near-optimal boundaries for the symbol decisions of the PAM-N signal. For reference level adaptation, the hamming distances between two consecutive data samples and their in-between edge sample are evaluated. Reference levels for symbol decisions are adjusted accordingly such that on a data transition, an edge sample has on average, equal hamming distance to its adjacent data samples. DC offset may be compensated to ensure detectable data transitions for reference level adaptation. AFE gains may be jointly adapted with sampler reference levels such that the difference between a reference level and a pre-determined target voltage is minimized.

公开(公告)号：US20210152402A1

公开(公告)日：2021-05-20

申请号：US17110530

申请日：2020-12-03

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Brian S. Leibowitz ,  Jade M. Kizer ,  Thomas H. Greer ,  Akash Bansal

IPC: H04L25/03 ,  H04B1/12

Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.