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    Constructions Comprising Stacked Memory Arrays
    212.
    发明申请
    Constructions Comprising Stacked Memory Arrays 审中-公开

    公开(公告)号：US20190006423A1

    公开(公告)日：2019-01-03

    申请号：US16103032

    申请日：2018-08-14

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli

    IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

    CPC classification number: H01L27/2481 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/71 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144

    Abstract: Some embodiments include a construction having a first memory array deck and a second memory array deck over the first memory array deck. The second memory array deck differs from the first memory array deck in one or more operating characteristics, in pitch, and/or in one or more structural parameters; with the structural parameters including different materials and/or different thicknesses of materials. Some embodiments include a construction having a first series and a third series of access/sense lines extending along a first direction, and a second series of access/sense lines between the first and third series and extending along a second direction which crosses the first direction. First memory cells are between the first and second series of access/sense lines and arranged in a first memory array deck. Second memory cells are between the second and third series of access/sense lines and arranged in a second memory array deck.

    MEMORY CELLS HAVING RESISTORS AND FORMATION OF THE SAME
    213.
    发明申请
    MEMORY CELLS HAVING RESISTORS AND FORMATION OF THE SAME 审中-公开

    公开(公告)号：US20180374900A1

    公开(公告)日：2018-12-27

    申请号：US15632536

    申请日：2017-06-26

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Andrea Redaelli ,  Agostino Pirovano ,  Innocenzo Tortorelli

    IPC: H01L27/24 ,  H01L45/00 ,  H01L49/02

    Abstract: The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first conductive line and the second conductive line. Forming the memory element can include forming one or more memory materials, and forming a resistor in series with the one or more memory materials. The resistor can be configured to reduce a capacitive discharge through the memory element during a state transition of the memory element.

    Apparatuses including memory cells and methods of operation of same
    214.
    发明授权
    Apparatuses including memory cells and methods of operation of same 有权

    公开(公告)号：US10163506B2

    公开(公告)日：2018-12-25

    申请号：US15841118

    申请日：2017-12-13

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Innocenzo Tortorelli ,  Andrea Redaelli ,  Fabio Pellizzer

    IPC: G11C11/00 ,  G11C13/00

    Abstract: Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first polarity and read with a read pulse having a second polarity. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities. The memory cell may exhibit reduced voltage drift and/or threshold voltage distribution. Described herein is a memory cell that acts as both a memory element and a selector device. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities.

    Constructions comprising stacked memory arrays
    218.
    发明授权
    Constructions comprising stacked memory arrays 有权

    公开(公告)号：US09691475B2

    公开(公告)日：2017-06-27

    申请号：US14662920

    申请日：2015-03-19

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli

    IPC: G11C13/00

    CPC classification number: H01L27/2481 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/71 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144

    Abstract: Some embodiments include a construction having a first memory array deck and a second memory array deck over the first memory array deck. The second memory array deck differs from the first memory array deck in one or more operating characteristics, in pitch, and/or in one or more structural parameters; with the structural parameters including different materials and/or different thicknesses of materials. Some embodiments include a construction having a first series and a third series of access/sense lines extending along a first direction, and a second series of access/sense lines between the first and third series and extending along a second direction which crosses the first direction. First memory cells are between the first and second series of access/sense lines and arranged in a first memory array deck. Second memory cells are between the second and third series of access/sense lines and arranged in a second memory array deck.

    Memory arrays
    219.
    发明授权
    Memory arrays 有权

    公开(公告)号：US09614007B2

    公开(公告)日：2017-04-04

    申请号：US14803303

    申请日：2015-07-20

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Andrea Redaelli

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2481 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

    Abstract: Some embodiments include a memory array having a first memory cell adjacent to a second memory cell along a lateral direction. The second memory cell is vertically offset relative to the first memory cell. Some embodiments include a memory array having a series of data/sense lines extending along a first direction, a series of access lines extending along a second direction, and memory cells vertically between the access lines and data/sense lines. The memory cells are arranged in a grid having columns along the first direction and rows along the second direction. Memory cells in a common column and/or row as one another are arranged in two alternating sets, with a first set having memory cells at a first height and a second set having memory cells at a second height vertically offset relative to the first height. Some embodiments include methods of forming memory arrays.

    Fuses, and Methods of Forming and Using Fuses
    220.
    发明申请
    Fuses, and Methods of Forming and Using Fuses 审中-公开
    保险丝，以及使用保险丝的方法

    公开(公告)号：US20170047187A1

    公开(公告)日：2017-02-16

    申请号：US15339699

    申请日：2016-10-31

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Giorgio Servalli

    IPC: H01H85/06 ,  G11C13/00 ,  H01H85/08

    CPC classification number: H01H85/06 ,  G11C13/0004 ,  H01H37/32 ,  H01H85/08 ,  H01H85/11 ,  Y10T29/49107

    Abstract: Some embodiments include a fuse having a tungsten-containing structure directly contacting an electrically conductive structure. The electrically conductive structure may be a titanium-containing structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Some embodiments include a method of forming and using a fuse. The fuse is formed to have a tungsten-containing structure directly contacting an electrically conductive structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Current exceeding the predetermined level is passed through the interface to rupture the interface.

    Abstract translation: 一些实施例包括具有直接接触导电结构的含钨结构的熔丝。 导电结构可以是含钛结构。 含钨结构和导电结构之间的界面被配置为当通过界面的电流超过预定水平时破裂。 一些实施例包括形成和使用保险丝的方法。 保险丝形成为具有直接接触导电结构的含钨结构。 含钨结构和导电结构之间的界面被配置为当通过界面的电流超过预定水平时破裂。 超过预定水平的电流通过界面破裂界面。

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