公开(公告)号：US11070128B2

公开(公告)日：2021-07-20

申请号：US16715209

申请日：2019-12-16

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana ,  Shivam Kalla

IPC: H02M3/07 ,  G11C16/30 ,  G11C5/14

Abstract: A charge pump circuit generates a charge pump output signal at a first node and is enabled by a charge pump control signal. A diode has first and second terminals coupled to first and second nodes. A comparator has an inverting input coupled to the second node and a non-inverting input coupled to a third node, and causes generation of the charge pump control signal. A first current mirror produces a first current at the second node, and a second current mirror produces a second current (equal in magnitude to the first current) at the third node. The first terminal and second terminals may be a cathode and an anode. The first current mirror may be a current sink sinking a first current from the second node. The second current mirror may be current source sourcing a second current (equal in magnitude to the first current) to the third node.

公开(公告)号：US11048525B2

公开(公告)日：2021-06-29

申请号：US16273704

申请日：2019-02-12

Applicant: STMicroelectronics Application GMBH ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Roberto Colombo ,  Om Ranjan

IPC: G06F13/36 ,  G06F9/445 ,  H04L9/06 ,  H04L9/32 ,  G06F11/10

Abstract: A processing system includes a plurality of configuration data clients, each associated with a respective address and including a respective register, and where a respective configuration data client is configured to receive a respective first configuration data and to store the respective first configuration data in the respective register; a hardware block coupled to at least one of the configuration data clients and configured to change operation as a function of the respective first configuration data stored in the respective registers; a non-volatile memory including second configuration data, where the second configuration data are stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients; and a hardware configuration circuit configured to sequentially read the data packets from the non-volatile memory and to transmit the respective first configuration data to the respective configuration data client.

公开(公告)号：US20210192070A1

公开(公告)日：2021-06-24

申请号：US16726498

申请日：2019-12-24

Applicant: STMicroelectronics International N.V.

Inventor： Dhulipalla Phaneendra KUMAR

IPC: G06F21/62

Abstract: A system includes a random number generator generating a random number in response to an event. Control logic generates hierarchical part alignment selectors from the random number. For each secure data block to be stored in volatile storage, a physical address of a first logical address for that secure data block is set based upon the hierarchical part alignment selectors. For each data word within that secure data block, a physical address of a first logical address for that data word is set based upon the hierarchical part alignment selectors. For each data byte within that data word, a physical address of a first logical address for that data byte is set based upon the hierarchical part alignment selectors. A physical address of a logical address for a first data bit within that data byte is set based upon the hierarchical part alignment selectors.

公开(公告)号：US11041905B2

公开(公告)日：2021-06-22

申请号：US16671933

申请日：2019-11-01

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma

IPC: G01R31/3185 ,  G06F11/267 ,  G06F11/27 ,  G01R31/3183 ,  G01R31/317

Abstract: A circuit includes a test data input (TDI) pin receiving a test data input signal, a test data out (TDO) pin outputting a test data output signal, and debugging test access port (TAP) having a test data input coupled to the TDI pin and a bypass register having an input coupled to the test data input of the debugging TAP. A multiplexer has inputs coupled to the TDI pin and the debugging TAP. A testing TAP has a test data input coupled to the output of the multiplexer, and a data register having an input coupled to the test data input of the testing TAP. The multiplexer switches so the test data input signal is selectively coupled to the input of the data register of the testing TAP so the output of the debugging TAP is selectively coupled to the input of the data register of the testing TAP.

公开(公告)号：US11025252B2

公开(公告)日：2021-06-01

申请号：US16578487

申请日：2019-09-23

Applicant: STMicroelectronics International N.V.

Inventor： Shishir Kumar ,  Tanuj Kumar ,  Deepak Kumar Bihani

IPC: H03K19/003

Abstract: A failure determination circuit includes a latch circuit that receives an internal clock from a clock latch that rises in response to an external clock rising. In response to a rising edge of the external clock, the circuit generates a rising edge of a fault flag. In response to a rising edge of the internal clock if it occurs, the fault flag falls. The fault flag is then latched. The latched fault flag indicates a single bit upset in the clock latch if the falling edge of the fault flag was not generated prior to latching, if the clock latch is in an active mode, and indicates a single bit upset in the clock latch if the falling edge of the fault flag was generated prior to latching, if the clock latch is in an inactive mode.

公开(公告)号：US10977854B2

公开(公告)日：2021-04-13

申请号：US16280963

申请日：2019-02-20

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Surinder Pal Singh ,  Thomas Boesch ,  Giuseppe Desoli

IPC: G06T7/11 ,  G06K9/00 ,  G06T15/08 ,  G06T7/62 ,  G06F16/901 ,  G06F9/38 ,  G06K9/62 ,  G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: Embodiments of a device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and at least one communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and a data volume sculpting unit, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting unit has a counter, a comparator, and a controller. The data volume sculpting unit is arranged to receive a stream of feature map data that forms a three-dimensional (3D) feature map. The 3D feature map is formed as a plurality of two-dimensional (2D) data planes. The data volume sculpting unit is also arranged to identify a 3D volume within the 3D feature map that is dimensionally smaller than the 3D feature map and isolate data from the 3D feature map that is within the 3D volume for processing in a deep learning algorithm.

公开(公告)号：US20210074340A1

公开(公告)日：2021-03-11

申请号：US17010704

申请日：2020-09-02

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Vivek TYAGI ,  Vikas RANA ,  Chantal AURICCHIO ,  Laura CAPECCHI

IPC: G11C7/12 ,  G11C7/06 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4094

Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.

公开(公告)号：US20210073450A1

公开(公告)日：2021-03-11

申请号：US17094743

申请日：2020-11-10

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Thomas BOESCH ,  Giuseppe DESOLI

IPC: G06F30/327 ,  G06N3/04 ,  G06N3/08 ,  G06F30/34 ,  G06N3/063 ,  G06F9/445 ,  G06F13/40 ,  G06F15/78

Abstract: Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs. The input port architectural composition is defined by a plurality of M data paths including A data inputs and B control inputs.

公开(公告)号：US10930650B2

公开(公告)日：2021-02-23

申请号：US16450141

申请日：2019-06-24

Applicant: STMicroelectronics International N.V.

Inventor： Vishal Kumar Sharma

IPC: H01L27/092 ,  H01L27/02 ,  H01L29/06

Abstract: In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures.

公开(公告)号：US20210006237A1

公开(公告)日：2021-01-07

申请号：US16460191

申请日：2019-07-02

Applicant: STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal

IPC: H03K3/037 ,  H03L7/00 ,  H03K19/21

Abstract: A synchronizer circuit includes a first synchronizer having a first input for receiving a signal associated with a first clock signal, a second input for receiving a second clock signal, and an output for providing a synchronizer circuit output signal; a second synchronizer having a first input for receiving the signal associated with the first clock signal, a second input for receiving the second clock signal, and an output; a detection stage having a first input coupled to the output of the first synchronizer and to the output of the second synchronizer, a second input for receiving the second clock signal, and an output; and a fault output stage having a first input coupled to the detection stage, a second input for receiving the second clock signal, and an output for providing a fault output signal.