WAFER LEVEL CHIP SCALE PACKAGE HAVING VARYING THICKNESSES

    公开(公告)号:US20230411332A1

    公开(公告)日:2023-12-21

    申请号:US18340380

    申请日:2023-06-23

    Inventor: Jing-En LUAN

    CPC classification number: H01L24/14 H01L23/49816

    Abstract: A wafer level chip scale package (WLCSP) with portions that have different thicknesses. A first passive surface of a die in the WLSCP includes a plurality of surfaces. The plurality of surfaces may include inclined surfaces or flat surfaces. Thicker portions of die, with more semiconductor material remaining are non-critical portions that increase a WLCSP's strength for further processing and handling after formation, and the thinner portions are critical portions that reduce a Coefficient of Thermal Expansion (CTE) mismatch between a WLCSP and a PCB.

    OXIDE FIELD TRENCH POWER MOSFET WITH A MULTI EPITAXIAL LAYER SUBSTRATE CONFIGURATION

    公开(公告)号:US20230135000A1

    公开(公告)日:2023-05-04

    申请号:US17962634

    申请日:2022-10-10

    Abstract: A semiconductor substrate includes: a base substrate layer doped with a first type dopant; a first epitaxial layer on the base substrate layer that has a first thickness and is doped with the first type dopant to provide a first resistivity; a second epitaxial layer on the first epitaxial layer that has a second thickness and is doped with the first type dopant to provide a second resistivity (less than the third resistivity); and a third epitaxial layer on the second epitaxial layer that has a third thickness and is doped with the first type dopant to provide a third resistivity (less than the second resistivity). An oxide field trench transistor includes a trench with insulated polygate and polysource regions extending into the semiconductor substrate and passing through the first doped region, the second doped region, the third epitaxial layer and partially into the second epitaxial layer.

    Multi-chip package
    224.
    发明授权

    公开(公告)号:US11581289B2

    公开(公告)日:2023-02-14

    申请号:US16935081

    申请日:2020-07-21

    Abstract: A multi-chip package including a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first side having a first conductive layer, a second side having a second conductive layer, and an edge, the first conductive layer coupled to the second conductive layer at a location adjacent to the edge. The second integrated circuit is coupled to the second conductive layer of the first integrated circuit.

    Semiconductor device with a dielectric between portions

    公开(公告)号:US11581232B2

    公开(公告)日:2023-02-14

    申请号:US16880684

    申请日:2020-05-21

    Inventor: Jing-En Luan

    Abstract: A semiconductor device having a channel between active sections or portions of the device is disclosed. An elastic material, such as dielectric or a polymer, is deposited into the channel and cured to increase flexibility and thermal expansion properties of the semiconductor device. The elastic material reduces the thermal and mechanical mismatch between the semiconductor device and the substrate to which the semiconductor device is coupled in downstream processing to improve reliability. The semiconductor device may also include a plurality of channels formed transverse with respect to each other. Some of the channels extend all the way through the semiconductor device, while other channels extend only partially through the semiconductor device.

    SENSOR PACKAGE WITH EMBEDDED INTEGRATED CIRCUIT

    公开(公告)号:US20230030627A1

    公开(公告)日:2023-02-02

    申请号:US17812679

    申请日:2022-07-14

    Inventor: Jing-En LUAN

    Abstract: Provided is a sensor package with an integrated circuit embedded in a substrate and a sensor die on the substrate. The substrate includes a molding compound that has additives configured to respond to a laser. The integrated circuit is embedded in the molding compound. An opening is through the substrate and is aligned with the sensor die. A lid covers the sensor die and the substrate, forming a cavity. At least one trace is formed on a first surface of the substrate, on an internal sidewall of the opening and on a second surface of the substrate with a laser direct structuring process.

    Gas sensors
    227.
    发明授权

    公开(公告)号:US11543378B2

    公开(公告)日:2023-01-03

    申请号:US16709811

    申请日:2019-12-10

    Abstract: The present disclosure is directed to a gas sensor that includes an active sensor area that is exposed to an environment for detection of elements. The gas sensor may be an air quality sensor that can be fixed in position or carried by a user. The gas sensor includes a heater formed above chamber. The gas sensor includes an active sensor layer above the heater that forms the active sensor area. The gas sensor can include a passive conductive layer, such as a hotplate that further conducts and distributes heat from the heater to the active sensor area. The heater can include a plurality of extensions. The heater can also include a first conductive layer and a second conductive layer on the first conductive layer where the second conductive layer includes a plurality of openings to increase an amount of heat and to more evenly distribute heat from the heater to the active sensor area.

    Molded proximity sensor
    229.
    发明授权

    公开(公告)号:US11513220B2

    公开(公告)日:2022-11-29

    申请号:US16562189

    申请日:2019-09-05

    Abstract: A proximity sensor includes a printed circuit board substrate, a semiconductor die, electrical connectors, a lens, a light emitting assembly, and an encapsulating layer. The semiconductor die is positioned over the printed circuit board substrate with its upper surface facing away from the printed circuit board substrate. Each of the electrical connectors is in electrical communication with a contact pad of the semiconductor die and a respective contact pad of the printed circuit board substrate. The lens is positioned over a sensor area of the semiconductor die. The light emitting assembly includes a light emitting device having a light emitting area, a lens positioned over the light emitting area, and contact pads facing the printed circuit board substrate. The encapsulating layer is positioned on the printed circuit board substrate, at least one of the electrical connectors, the semiconductor die, the lens, and the light emitting assembly.

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