公开(公告)号：US11328986B2

公开(公告)日：2022-05-10

申请号：US16554288

申请日：2019-08-28

Applicant: INTEL CORPORATION

Inventor： Aleksandar Aleksov ,  Feras Eid ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/00 ,  H01L23/495

Abstract: Disclosed herein are capacitor-wirebond pad structures for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a die and an IC package support. The IC package support may include a capacitor, and the capacitor may include a first capacitor plate, a second capacitor plate, and a capacitor dielectric between the first capacitor plate and the second capacitor plate. The die may be wirebonded to the first capacitor plate.

公开(公告)号：US11316497B2

公开(公告)日：2022-04-26

申请号：US16707497

申请日：2019-12-09

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H03H9/54 ,  H03H9/02 ,  H03H9/64

Abstract: Embodiments may relate to a die such as an acoustic wave resonator (AWR) die. The die may include a first filter and a second filter in the die body. The die may further include an electromagnetic interference (EMI) structure that surrounds at least one of the filters. Other embodiments may be described or claimed.

公开(公告)号：US20220093725A1

公开(公告)日：2022-03-24

申请号：US17025209

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mohammad Enamul Kabir ,  Zhiguo Qian ,  Gerald S. Pasdast ,  Kimin Jun ,  Shawna M. Liff ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Feras Eid

IPC: H01L49/02 ,  H01L23/49 ,  H01L23/492

Abstract: Disclosed herein are capacitors and resistors at direct bonding interfaces in microelectronic assemblies, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component, wherein a direct bonding interface of the second microelectronic component is direct bonded to a direct bonding interface of the first microelectronic component, the microelectronic assembly includes a sensor, the sensor includes a first sensor plate and a second sensor plate, the first sensor plate is at the direct bonding interface of the first microelectronic component, and the second sensor plate is at the direct bonding interface of the second microelectronic component.

公开(公告)号：US20220093531A1

公开(公告)日：2022-03-24

申请号：US17544651

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Feras Eid ,  Veronica Aleman Strong ,  Aleksandar Aleksov ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: H01L23/60 ,  H01L23/498 ,  H01L21/48 ,  H01H61/01 ,  H01H49/00

Abstract: A switch in a package substrate of a microelectronic package is provided, the switch comprising: an actuator plate; a strike plate; and a connecting element mechanically coupling the actuator plate and the strike plate. The switch is configured to move within a cavity inside the package substrate between an open position and a closed position, a conductive material is coupled to the switch and to a ground via in the package substrate, and the conductive material is configured to move with the switch, such that the switch is conductively coupled to the ground via in the open position and the closed position.

公开(公告)号：US20220093492A1

公开(公告)日：2022-03-24

申请号：US17025771

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Krishna Bharath ,  Han Wui Then ,  Kimin Jun ,  Aleksandar Aleksov ,  Mohammad Enamul Kabir ,  Shawna M. Liff ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/49 ,  H05K1/11 ,  H01L23/538 ,  H01L23/532

Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.

公开(公告)号：US20220084962A1

公开(公告)日：2022-03-17

申请号：US17024307

申请日：2020-09-17

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Kristof Darmawikarta ,  Benjamin Duong ,  Telesphor Kamgaing ,  Miranda Ngan ,  Srinivas Pietambaram

IPC: H01L23/66 ,  H05K1/02 ,  H01P3/08 ,  H01Q1/22 ,  H01L25/065 ,  H01L25/00

Abstract: An electronic assembly, such as an integrated circuit package, may be formed comprising a package substrate, a plurality of integrated circuit devices electrically attached to the package substrate, wherein each integrated circuit device of the plurality of integrated circuit devices includes an active surface and a backside surface, and wherein a first integrated circuit device and a second integrated circuit device of the plurality of integrated circuit devices includes radio frequency logic circuitry and a radio frequency antenna formed in or attached thereto, and a radio frequency waveguide on the backside surface of the first integrated circuit device and on the backside surface of the second integrated circuit device.

公开(公告)号：US11257745B2

公开(公告)日：2022-02-22

申请号：US16641219

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Aleksandar Aleksov ,  Veronica Strong ,  Kristof Darmawikarta ,  Arnab Sarkar

IPC: H05K1/00 ,  H05K1/03 ,  H05K1/09 ,  H05K1/11 ,  H05K1/18 ,  H05K3/02 ,  H05K3/10 ,  H05K3/40 ,  H05K3/46 ,  H01L21/00 ,  H01L21/02 ,  H01L21/31 ,  H01L21/44 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/70 ,  H01L21/469 ,  H01L21/4763 ,  H01L21/8246 ,  H01L23/00 ,  H01L23/28 ,  H01L23/31 ,  H01L23/48 ,  H01L23/52 ,  H01L23/58 ,  H01L23/485 ,  H01L23/495 ,  H01L23/498 ,  H01L23/522 ,  G06K19/02 ,  G06K19/077 ,  H05K3/18

Abstract: A package substrate, comprising a package comprising a substrate, the substrate comprising a dielectric layer, a via extending to a top surface of the dielectric layer; and a bond pad stack having a central axis and extending laterally from the via over the first layer. The bond pad stack is structurally integral with the via, wherein the bond pad stack comprises a first layer comprising a first metal disposed on the top of the via and extends laterally from the top of the via over the top surface of the dielectric layer adjacent to the via. The first layer is bonded to the top of the via and the dielectric layer, and a second layer is disposed over the first layer. A third layer is disposed over the second layer. The second layer comprises a second metal and the third layer comprises a third metal. The second layer and the third layer are electrically coupled to the via.

公开(公告)号：US11239155B2

公开(公告)日：2022-02-01

申请号：US16724346

申请日：2019-12-22

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Feras Eid ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Veronica Aleman Strong

IPC: H01L23/522 ,  H01L23/498 ,  H01L23/528 ,  H01L23/552 ,  H01L23/00 ,  H01L27/02

Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC component may include a conductive contact structure that includes a first contact element and a second contact element. The first contact element may be exposed at a face of the IC component, the first contact element may be between the face of the IC component and the second contact element, the second contact element may be spaced apart from the first contact element by a gap, and the second contact element may be in electrical contact with an electrical pathway in the IC component.

公开(公告)号：US11133263B2

公开(公告)日：2021-09-28

申请号：US16573948

申请日：2019-09-17

Applicant: Intel Corporation

Inventor： Veronica Strong ,  Aleksandar Aleksov ,  Henning Braunisch ,  Brandon Rawlings ,  Johanna Swan ,  Shawna Liff

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L21/48 ,  H05K1/18

Abstract: An integrated circuit package may be formed including at least one die side integrated circuit device having an active surface electrically attached to an electronic interposer, wherein the at least one die side integrated circuit device is at least partially encased in a mold material layer and wherein a back surface of the at least one die side integrated circuit device is in substantially the same plane as an outer surface of the mold material layer. At least one stacked integrated circuit device may be electrically attached to the back surface of the at least one die side integrated circuit through an interconnection structure formed between the at least one die side integrated circuit device and the at least one stacked integrated circuit device.

公开(公告)号：US11107781B2

公开(公告)日：2021-08-31

申请号：US16481392

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Rahul N. Manepalli ,  Kristof Kuwawi Darmawikarta ,  Robert Alan May ,  Aleksandar Aleksov ,  Telesphor Kamgaing

IPC: H01L23/66 ,  H01L21/56 ,  H01L23/00

Abstract: Semiconductor packages having a die electrically connected to an antenna by a coaxial interconnect are described. In an example, a semiconductor package includes a molded layer between a first antenna patch and a second antenna patch of the antenna. The first patch may be electrically connected to the coaxial interconnect, and the second patch may be mounted on the molded layer. The molded layer may be formed from a molding compound, and may have a stiffness to resist warpage during fabrication and use of the semiconductor package.