中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

374 records (took 0.025 seconds)

    Methods and apparatus to parallelize data decompression
    222.
    发明授权
    Methods and apparatus to parallelize data decompression 有权

    公开(公告)号：US11258459B2

    公开(公告)日：2022-02-22

    申请号：US16996012

    申请日：2020-08-18

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  James D. Guilford ,  Sudhir K. Satpathy ,  Sanu K. Mathew

    IPC: H03M7/00 ,  H03M7/30 ,  H03M7/40

    Abstract: Methods and apparatus to parallelize data decompression are disclosed. An example method selecting initial starting positions in a compressed data bitstream; adjusting a first one of the initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; outputting first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position; and merging the first decoded data with second decoded data generated by decoding a second segment of the bitstream, the decoding of the second segment starting from a second position in the bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the bitstream.

    APPARATUSES, METHODS, AND SYSTEMS FOR HASHING INSTRUCTIONS
    225.
    发明申请
    APPARATUSES, METHODS, AND SYSTEMS FOR HASHING INSTRUCTIONS 有权

    公开(公告)号：US20210049013A1

    公开(公告)日：2021-02-18

    申请号：US17087536

    申请日：2020-11-02

    Applicant: Intel Corporation

    Inventor： Regev Shemy ,  Zeev Sperber ,  Wajdi Feghali ,  Vinodh Gopal ,  Amit Gradstein ,  Simon Rubanovich ,  Sean Gulley ,  Ilya Albrekht ,  Jacob Doweck ,  Jose Yallouz ,  Ittai Anati

    IPC: G06F9/30 ,  G06F9/38 ,  H04L9/06

    Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described. In one embodiment, a processor includes a decode circuit to decode a single instruction into a decoded single instruction, the single instruction including at least one first field that identifies eight 32-bit state elements A, B, C, D, E, F, G, and H for a round according to a SM3 hashing standard and at least one second field that identifies an input message; and an execution circuit to execute the decoded single instruction to: rotate state element C left by 9 bits to form a rotated state element C, rotate state element D left by 9 bits to form a rotated state element D, rotate state element G left by 19 bits to form a rotated state element G, rotate state element H left by 19 bits to form a rotated state element H, perform two rounds according to the SM3 hashing standard on the input message and state element A, state element B, rotated state element C, rotated state element D, state element E, state element F, rotated state element G, and rotated state element H to generate an updated state element A, an updated state element B, an updated state element E, and an updated state element F, and store the updated state element A, the updated state element B, the updated state element E, and the updated state element F into a location specified by the single instruction.

    Efficient length limiting of compression codes
    227.
    发明授权
    Efficient length limiting of compression codes 有权

    公开(公告)号：US10694217B2

    公开(公告)日：2020-06-23

    申请号：US16137985

    申请日：2018-09-21

    Applicant: Intel Corporation

    Inventor： Sudhir K. Satpathy ,  Vinodh Gopal ,  James D. Guilford ,  Sanu K. Mathew ,  Vikram B. Suresh

    IPC: H04N19/96 ,  H03M7/40 ,  H04N19/13

    Abstract: A processing device includes compression circuitry to encode an input stream with an encoding that translates multiple symbols of fixed length into multiple codes of variable length between one and a maximum length, to generate a compressed stream. The compression circuitry is to: determine at least a first symbol of the multiple symbols having a first code that exceeds the maximum length; identify a short code of the multiple codes that is to be lengthened to provide an increased encoding capacity for the at least the first symbol; generate multiple code-length converted values including to increase the length of the short code to the maximum length and decrease, to the maximum length, a length of the first code of the at least the first symbol; and generate, with use of the set of code-length converted values, the compressed stream at the output terminal.

    Instructions and logic to provide SIMD SM3 cryptographic hashing functionality
    228.
    发明授权
    Instructions and logic to provide SIMD SM3 cryptographic hashing functionality 有权

    公开(公告)号：US10592245B2

    公开(公告)日：2020-03-17

    申请号：US15600200

    申请日：2017-05-19

    Applicant: Intel Corporation

    Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Sean M. Gulley ,  Kirk S. Yap ,  Wajdi K. Feghali

    IPC: G06F9/30 ,  G06F21/72

    Abstract: Instructions and logic provide SIMD SM3 cryptographic hashing functionality. Some embodiments include a processor comprising: a decoder to decode instructions for a SIMD SM3 message expansion, specifying first and second source data operand sets, and an expansion extent. Processor execution units, responsive to the instruction, perform a number of SM3 message expansions, from the first and second source data operand sets, determined by the specified expansion extent and store the result into a SIMD destination register. Some embodiments also execute instructions for a SIMD SM3 hash round-slice portion of the hashing algorithm, from an intermediate hash value input, a source data set, and a round constant set. Processor execution units perform a set of SM3 hashing round iterations upon the source data set, applying the intermediate hash value input and the round constant set, and store a new hash value result in a SIMD destination register.

    System-on-chip (SoC) to perform a bit range isolation instruction
    229.
    发明授权
    System-on-chip (SoC) to perform a bit range isolation instruction 有权

    公开(公告)号：US10579380B2

    公开(公告)日：2020-03-03

    申请号：US14568754

    申请日：2014-12-12

    Applicant: Intel Corporation

    Inventor： Maxim Loktyukhin ,  Eric W Mahurin ,  Bret L Toll ,  Martin G Dixon ,  Sean P Mirkes ,  David L Kreitzer ,  Elmoustapha Ould-Ahmed-Vall ,  Vinodh Gopal

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.

Patent Agency Ranking