公开(公告)号：US20230037420A1

公开(公告)日：2023-02-09

申请号：US17386062

申请日：2021-07-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Brett T. Cucci ,  Jeonghyun Hwang ,  Siva P. Adusumilli

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/778

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a gate structure comprising a horizontal portion and a substantially vertical stem portion; and an air gap surrounding the substantially vertical stem portion and having a curved surface under the horizontal portion.

公开(公告)号：US11574867B2

公开(公告)日：2023-02-07

申请号：US17104078

申请日：2020-11-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ephrem G. Gebreselasie ,  Vibhor Jain ,  Yves T. Ngu ,  Johnatan A. Kantarovsky ,  Alain F. Loiseau

IPC: H01L23/52 ,  H01L23/525 ,  H01L21/8249 ,  H01L21/02 ,  H01L27/07 ,  H01L23/62 ,  H01L27/115 ,  H01L27/112 ,  H01L27/02

Abstract: An electrical fuse (e-fuse) includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The fuse link may be formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor. The gate conductor may control a current source for programming the e-fuse. The e-fuse reduces the footprint and the required programming energy compared to conventional e-fuses.

公开(公告)号：US20230029507A1

公开(公告)日：2023-02-02

申请号：US17391031

申请日：2021-08-02

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： YONGSHUN SUN ,  SHYUE SENG TAN ,  ENG HUAT TOH ,  XINSHU CAI

IPC: H01L29/788 ,  H01L29/161 ,  H01L29/10 ,  H01L29/66

Abstract: A nonvolatile memory device is provided. The nonvolatile memory device comprises an n-doped source, an n-doped drain, and a doped region in a first p-well in a substrate. A floating gate may be arranged over the first p-well, whereby the doped region may be arranged at least partially under the floating gate.

公开(公告)号：US11569170B2

公开(公告)日：2023-01-31

申请号：US17064602

申请日：2020-10-07

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Siva P. Adusumilli ,  Mark David Levy ,  Ramsey Hazbun ,  Alvin Joseph ,  Steven Bentley

IPC: H01L23/535 ,  H01L21/74 ,  H01L21/768 ,  H01L23/367 ,  H01L23/48 ,  H01L29/10 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/778 ,  H01L29/735

Abstract: A semiconductor device is provided, the semiconductor device comprising a substrate having merged cavities in the substrate. An active region is over the merged cavities in the substrate. A thermally conductive layer is in the merged cavities in the substrate, whereby the thermally conductive layer at least partially fills up the merged cavities in the substrate. A first contact pillar connects the thermally conductive layer in the merged cavities in the substrate with a metallization layer above the active region.

公开(公告)号：US11569108B2

公开(公告)日：2023-01-31

申请号：US16901099

申请日：2020-06-15

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michael Raga-Barone

IPC: H01L21/673 ,  G03F7/20

Abstract: An illustrative device disclosed herein includes a plate and a reticle pod receiving structure on the front surface of the plate that at least partially bounds a reticle pod receiving area on the front surface. In this example, the back surface of the plate has a pin engagement structure that is adapted to engage a plurality of pins and a fluid flow channel that is adapted to allow fluid communication with an interior region of a reticle pod when the reticle pod is positioned in the reticle pod receiving area.

公开(公告)号：US11567277B1

公开(公告)日：2023-01-31

申请号：US17472846

申请日：2021-09-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Mark Levy ,  Siva P. Adusumilli

IPC: G02B6/43 ,  G02B6/42

Abstract: Structures that include a distributed Bragg reflector and methods of fabricating a structure that includes a distributed Bragg reflector. The structure includes a substrate, an optical component, and a distributed Bragg reflector positioned between the optical component and the substrate. The distributed Bragg reflector includes airgaps and silicon layers that alternate in a vertical direction with the airgaps to define a plurality of periods.

公开(公告)号：US11567260B1

公开(公告)日：2023-01-31

申请号：US17501508

申请日：2021-10-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Won Suk Lee ,  Lin Jiang ,  Colleen Meagher

IPC: G02B6/122 ,  G02B6/36 ,  H01L31/0232

Abstract: Structures including an optical component and methods of forming a structure including an optical component. The structure includes an optical component on a substrate, and a back-end-of-line stack including multiple metal levels. Each of the metal levels includes a dielectric layer and metal features positioned over the optical component as metal fill in the dielectric layer. The metal features in at least two of the metal levels are arranged to overlap such that the optical component is fully covered normal to the substrate.

公开(公告)号：US20230027045A1

公开(公告)日：2023-01-26

申请号：US17383445

申请日：2021-07-23

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Jie ZENG ,  Raunak KUMAR ,  Souvick MITRA

IPC: H01L29/861 ,  H01L27/02 ,  H01L29/735 ,  H01L29/66

Abstract: An electrostatic discharge (ESD) protection device including: a substrate including: a first, second and third doped regions, the second doped region disposed between the first and third doped regions, the second doped region has a first conductivity type and a first doping concentration and the first and third doped regions have a second conductivity type and a second doping concentration; first and second doped terminal regions disposed within the first and second doped regions, respectively; and a doped island region disposed within the second doped region, the first and second doped terminal regions and doped island region have the second conductivity type and a third doping concentration, the third doping concentration higher than the first and second doping concentrations; and conductive terminals respectively coupled to the doped terminal regions; and an insulation layer arranged on the substrate between the conductive terminals and covering at least the second doped region.

公开(公告)号：US20230014455A1

公开(公告)日：2023-01-19

申请号：US17375166

申请日：2021-07-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hemant M. Dixit ,  Vinayak Bharat Naik ,  Kazutaka Yamane ,  Eng Huat Toh

IPC: G01R33/09 ,  G01R33/00

Abstract: A magnetic field sensor may include a plurality of MTJ elements. Each MTJ element of has a state indicated by a magnetic moment direction of a sensing layer relative to a pinned, reference layer in an absence of an external magnetic field. The plurality of MTJ elements are arranged into two identical sets of at least two MTJ elements, where each MTJ element in each respective set has a different state. The states of the MTJ elements are arranged in a manner to measure the external magnetic field regardless of the direction of the external magnetic field. The MTJ elements include identical layers, and are electrically serially connected.

公开(公告)号：US20230011972A1

公开(公告)日：2023-01-12

申请号：US17931933

申请日：2022-09-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Roderick A. Augur ,  Michal Rakowski ,  Kenneth J. Giewont ,  Karen A. Nummy

IPC: H01S5/20 ,  H01S5/30 ,  H01S5/223

Abstract: A laser structure, including: a dielectric matrix formed of a first material; a laser source formed within the dielectric matrix and formed of a semiconductor material; and a plurality of side confining features formed within the dielectric matrix and extending parallel to and along a length of the laser source. The plurality of side confining features are formed of the semiconductor material.