Field effect transistor with asymmetric gate structure and method

    公开(公告)号:US11342453B2

    公开(公告)日:2022-05-24

    申请号:US16996010

    申请日:2020-08-18

    Abstract: Disclosed is a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a replacement metal gate (RMG) structure that includes a first section, which traverses a semiconductor body at a channel region in a first-type well, and a second section, which is adjacent to the first section and which traverses the semiconductor body at a drain drift region in a second-type well. The RMG structure includes, in both sections, a first-type work function layer and a second-type work function layer on the first-type work function layer. However, the thickness of the first-type work function layer in the first section is greater than the thickness in the second section such that the RMG structure is asymmetric. Thus, threshold voltage (Vt) at the first section is greater than Vt at the second section and the LDMOSFET has a relatively high breakdown voltage (BV). Also disclosed are methods for forming the LDMOSFET.

    WAVEGUIDE CROSSINGS INCLUDING A SEGMENTED WAVEGUIDE SECTION

    公开(公告)号:US20220146748A1

    公开(公告)日:2022-05-12

    申请号:US17094105

    申请日:2020-11-10

    Inventor: Yusheng Bian

    Abstract: Structures with waveguide cores in multiple levels and methods of fabricating a structure that includes waveguide cores in multiple levels. The structure includes a first waveguide core and a second waveguide core positioned in a different level than the first waveguide core. The first waveguide core includes a longitudinal axis and a plurality of segments having a spaced arrangement along the longitudinal axis. The second waveguide core is aligned to extend across the plurality of segments of the first waveguide core.

    Concurrent manufacture of field effect transistors and bipolar junction transistors with gain tuning

    公开(公告)号:US11322414B2

    公开(公告)日:2022-05-03

    申请号:US16720084

    申请日:2019-12-19

    Abstract: Bipolar junction transistors include a collector, a base on the collector, and an emitter on the base. The base is between the collector and the emitter. The emitter comprises first portions and a second portion on the base. The first portions of the emitter are between the second portion of the emitter and the base. The first portions and the second portion comprise doped areas that are doped with the same polarity impurity in different concentrations. The base comprises a doped area that is doped with an opposite polarity impurity from the first and second portions of the emitter. The first portions of the emitter extend from the second portion of the emitter into the base. Specifically, the second portion has a bottom surface contacting the base, and the first portions comprise at least two separate impurity regions extending from the bottom surface of the second portion into the base.

    Single-rail memory circuit with row-specific voltage supply lines and boost circuits

    公开(公告)号:US11322200B1

    公开(公告)日:2022-05-03

    申请号:US17120325

    申请日:2020-12-14

    Abstract: A single-rail memory circuit includes an array of memory cells arranged in rows and columns and peripheral circuitry connected to the array for facilitating read and write operations with respect to selected memory cells. The peripheral circuitry includes, but is not limited to, boost circuits for the rows. Each boost circuit is connected to a wordline for a row and to a discrete voltage supply line for the same row. Each boost circuit for a row is configured to increase the voltage levels on the wordline and the voltage supply line for the row during a read of any selected memory cell within the row. Increasing the voltage levels on the wordline and on the voltage supply line during the read operation effectively boosts the read current. A method of operating the memory circuit reduces the probability of a read fail.

    STRUCTURE AND METHOD FOR CONTROLLING ELECTROSTATIC DISCHARGE (ESD) EVENT IN RESISTOR-CAPACITOR CIRCUIT

    公开(公告)号:US20220131369A1

    公开(公告)日:2022-04-28

    申请号:US17082182

    申请日:2020-10-28

    Abstract: Embodiments of the disclosure provide a circuit structure and method to control electrostatic discharge (ESD) events in a resistor-capacitor (RC) circuit. Circuit structures according to the disclosure may include a trigger transistor coupled in parallel with the RC circuit, and a gate terminal coupled to part of the RC circuit. A mirror transistor coupled in parallel with the RC circuit transmits a current that is less than a current through the trigger transistor. A snapback device has a gate terminal coupled to a source or drain of the mirror transistor, and a pair of anode/cathode terminals coupled in parallel with the RC circuit. A current at the gate terminal of the snapback device, derived from current in the mirror transistor, controls an anode/cathode current flow in the snapback device.

    ENLARGED WAVEGUIDE FOR PHOTONIC INTEGRATED CIRCUIT WITHOUT IMPACTING INTERCONNECT LAYERS

    公开(公告)号:US20220128762A1

    公开(公告)日:2022-04-28

    申请号:US17082291

    申请日:2020-10-28

    Abstract: Structures and methods implement an enlarged waveguide. The structure may include a semiconductor-on-insulator (SOI) substrate including a semiconductor-on-insulator (SOI) layer over a buried insulator layer over a semiconductor substrate. An inter-level dielectric (ILD) layer is over the SOI substrate. A first waveguide has a lower surface extending at least partially into the buried insulator layer, which allows vertical enlargement of the waveguide, without increasing the thickness of the ILD layer or increasing the length of interconnects to other devices. The enlarged waveguide may include nitride, and can be implemented with other conventional silicon and nitride waveguides.

    Photodiode and/or PIN diode structures

    公开(公告)号:US11316064B2

    公开(公告)日:2022-04-26

    申请号:US16887375

    申请日:2020-05-29

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one fin including substrate material, the at least one fin including sidewalls and a top surface; a trench on opposing sides of the at least one fin; a first semiconductor material lining the sidewalls and the top surface of the at least one fin, and a bottom surface of the trench; a photosensitive semiconductor material on the first semiconductor material and at least partially filling the trench; and a third semiconductor material on the photosensitive semiconductor material.

    ENERGY RECOVERY SYSTEM FOR A SEMICONDUCTOR FABRICATION FACILITY

    公开(公告)号:US20220113060A1

    公开(公告)日:2022-04-14

    申请号:US17556762

    申请日:2021-12-20

    Inventor: Thomas Huang

    Abstract: One illustrative energy recovery system disclosed herein includes a facility and a closed chilled water loop including a chilled water stream delivered to the facility and a returning water stream that is received from the facility. In this example, the system also includes a primary heat exchanger having a first fluid side and a second fluid side, the first fluid side is adapted to receive supply water and the second fluid side is adapted to receive at least a portion of the returning return water stream. The primary heat exchanger is adapted to effectuate heat transfer between the supply water flowing in the first fluid side and the returning water stream flowing in the second fluid side.

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