公开(公告)号：US20030090591A1

公开(公告)日：2003-05-15

申请号：US10243081

申请日：2002-09-12

Applicant: STMicroelectronics S.r.I.

Inventor： Davide Concion ,  Emiliano Piccinelli ,  Danilo Pau

IPC: H04N005/14

CPC classification number: H04N19/40 ,  H04N19/59

Abstract: A process for format conversion of DCT macroblocks in an MPEG video bitstream that are divided into blocks, each of which includes a plurality of microblocks. In each DCT block, the significant frequencies are identified and preserved, isolating a corresponding microblock preferably consisting of the microblock on the top left of each block and setting to zero the coefficients of the remaining microblocks. On the microblock thus isolated there is performed an inverse discrete cosine transform, and the microblock thus obtained is merged with the homologous microblocks obtained from the other blocks comprised in a respective starting macroblock, so as to give rise to a merging block. The merging block thus obtained undergoes a discrete cosine transform so as to obtain a final block, which can be assembled into a macroblock with converted format.

Abstract translation: MPEG视频比特流中的DCT宏块的格式转换处理，被分成块，每个块包括多个微块。 在每个DCT块中，识别和保存有效频率，隔离优选地由每个块的左上角的微块组成的相应微块，并将剩余微块的系数设置为零。 在这样隔离的微块上，执行逆离散余弦变换，并且由此获得的微块与从包含在相应起始宏块中的其他块获得的同源微块合并，以产生合并块。 如此获得的合并块经历离散余弦变换，以获得最终的块，其可以被组合成具有转换格式的宏块。

公开(公告)号：US20030080804A1

公开(公告)日：2003-05-01

申请号：US09998902

申请日：2001-10-31

Applicant: STMicroelectronics S.r.I.

Inventor： Davide Torrisi ,  Ignazio Martines

IPC: G05F001/10

CPC classification number: H02M3/073 ,  H02M2003/071 ,  H02M2003/075

Abstract: A negative charge pump circuit includes a cascade connection of a plurality of charge pump stages, each stage including at least a charge capacitance and a pass transistor driven by a corresponding phase signal. An input stage may be coupled to an input reference potential. An output stage may include an output terminal for generating a first pumped voltage. In addition, the charge pump circuit may further include a second output stage connected downstream to the input stage and including a second output terminal for generating a second pumped potential. The architecture may also be implemented in positive charge pump circuits.

Abstract translation: 负电荷泵电路包括多个电荷泵级的级联，每级包括至少一个充电电容和由相应的相位信号驱动的通过晶体管。 输入级可以耦合到输入参考电位。 输出级可以包括用于产生第一泵送电压的输出端子。 此外，电荷泵电路还可以包括连接到输入级的下游的第二输出级，并且包括用于产生第二泵浦电位的第二输出端。 该结构也可以在正电荷泵电路中实现。

公开(公告)号：US20030071689A1

公开(公告)日：2003-04-17

申请号：US10244113

申请日：2002-09-13

Applicant: STMicroelectronics S.r.I.

Inventor： Antonio Magazzu ,  Benedetto Marco Marletta ,  Giuseppe Gramegna ,  Alessandro D'Aquila

IPC: H03L007/00

CPC classification number: H03K17/162 ,  H03L7/0891 ,  H03L7/183

Abstract: A method and a circuit for minimizing glitches in phase-locked loops is presented. The circuit includes an input terminal connected to an input of a phase detector; a series of a charge pump generator, a filter and a voltage controlled oscillator connected downstream of the phase detector; and a frequency divider feedback connected between an output of the voltage controlled oscillator and a second input of the phase detector. The circuit provides for the inclusion of a compensation circuit connected between the charge pump generator and the filter to absorb an amount of the charge passed therethrough. This compensation circuit includes a storage element connected in series to two switches. The first switch is coupled to and controlled by an output of the charge pump and the second switch is coupled to and controlled by an output of a phase detector.

公开(公告)号：US20030068037A1

公开(公告)日：2003-04-10

申请号：US09974176

申请日：2001-10-10

Applicant: STMicroelectronics S.r.I.

Inventor： Guido Bertoni ,  Luca Breveglieri ,  Pasqualina Fragneto

IPC: H04L009/00

CPC classification number: G06F7/724

Abstract: A circuit for computing the inner of scalar product of two vectors in a finite Galois field defined by a generator polynomial, wherein each vector includes at least two elements belonging to said finite field, comprises one or more look-up tables storing digital words indicative of said possible combinations and said possible reductions. The digital words in question are defined as a function of the second elements of said vectors and the generator polynomial of the field. The input register(s) and the look-up table(s) are configured to co-operate in a plurality of subsequent steps to generate at each step a partial product result identified by at least one of digital word addressed in a corresponding look-up table as a function of the digital signals stored in the input register(s). The circuit also includes an accumulator unit for adding up the partial results generated at each step to give a final product result deriving from accumulation of said partial results.

Abstract translation: 一种用于计算由生成多项式定义的有限伽罗瓦域中的两个向量的标量积的内部的电路，其中每个向量包括属于所述有限域的至少两个元素，包括一个或多个查找表，其存储指示 说可能的组合和所述可能的减少。 所讨论的数字词被定义为所述向量的第二元素和场的生成多项式的函数。 输入寄存器和查找表被配置为在多个后续步骤中协作以在每个步骤处生成由相应查找表中寻址的数字字中的至少一个标识的部分乘积结果， 作为存储在输入寄存器中的数字信号的函数。 该电路还包括用于将在每个步骤产生的部分结果相加以产生从所述部分结果的积累得到的最终产品结果的累加器单元。

公开(公告)号：US20030032244A1

公开(公告)日：2003-02-13

申请号：US10261987

申请日：2002-10-01

Applicant: STMicroelectronics S.r.I.

Inventor： Daniela Peschiaroli ,  Alfonso Maurelli ,  Elisabetta Palumbo ,  Fausto Piazza

IPC: H01L021/336

CPC classification number: H01L27/11526 ,  H01L27/1052 ,  H01L27/11541

Abstract: A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the semiconductor substrate, and a plurality of memory cells in a third portion of the semiconductor substrate. A matrix mask used for selectively removing a dielectric layer from the first and third portions of the semiconductor substrate allows dielectric to remain on a floating gate of the plurality of memory cells and on the gate electrodes of the plurality of first transistors. A control gate is then formed on the floating gate, which is separated by the dielectric. Portions of the gate electrodes for the plurality of first transistors are left free so that contact is made with the transistors.

公开(公告)号：US20030026498A1

公开(公告)日：2003-02-06

申请号：US10171793

申请日：2002-06-14

Applicant: STMicroelectronics, S.r.I.

Inventor： Daniele Sirtori ,  Matteo Maravita

IPC: G06K009/40 ,  G06K009/64

CPC classification number: H04N7/012

Abstract: The conversion into a progressive format of digital images organized in half-frames or fields with interlaced lines or rows envisages selecting successive lines in one or more of said fields and reconstructing by pixels an image line set between the interlaced lines selected. The reconstruction operation obtains the image by creating a set of candidate patterns associated to the work window by selecting the patterns to be considered within the window. Next, applying to the patterns of the aforesaid set a first cost function which is representative of the correlations between pairs of pixels. Applying to the patterns of the aforesaid set a second cost function which is representative of the non-correlations between pairs of pixels. Selecting, for each candidate pattern, respective internal correlations and external non-correlations, calculating corresponding scores for the candidate patterns using the aforesaid first cost function. Selecting a best pattern by comparing the respective scores of the candidate patterns with at least one threshold; and selecting the pixels of the window identified by the best pattern selected, then reconstructing the missing line by filtration starting from said pixels.

Abstract translation: 以半帧或具有交错行或行的场的数字图像的逐行格式的转换设想在一个或多个所述场中选择连续的行，并且通过像素重建在所选择的交织行之间设置的图像行。 重建操作通过选择在窗口内考虑的模式来创建与工作窗口相关联的一组候选模式来获得图像。 接下来，应用上述的图案设置表示像素对之间的相关性的第一成本函数。 应用上述的图案设置表示像素对之间的非相关性的第二成本函数。 对于每个候选模式，选择各自的内部相关性和外部非相关性，使用前述第一成本函数计算候选模式的相应分数。 通过将候选模式的各个分数与至少一个阈值进行比较来选择最佳模式; 并选择由所选择的最佳图案标识的窗口的像素，然后从所述像素开始重新构建缺失的线。

公开(公告)号：US20030018861A1

公开(公告)日：2003-01-23

申请号：US10159782

申请日：2002-05-30

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Massimiliano Picca ,  Roberto Ravasio ,  Stefano Zanardi

IPC: G06F012/00

CPC classification number: G06F11/1072 ,  G11C2211/5641

Abstract: A method for error control in multilevel memory cells storing a configurable number of bits. The error control is performed using an error-control code which operates, in the encoding phase, on b-bit binary strings made up of k symbols of r-bit data. When the memory cells store a number r of bits, a data symbol is formed only with the data bits stored in a memory cell. When the memory cells store a number s of bits smaller than r, a data symbol is formed with the data bits stored in a memory cell and with r-s bits having a pre-determined logic value, in which the data bits stored in the memory cell are arranged in the least significant part of the data symbol, and the r-s bits having a pre-determined logic value are arranged in the most significant part of the data symbol.

Abstract translation: 一种用于存储可配置位数的多电平存储单元中的误差控制的方法。 使用在编码阶段中对由r位数据的k个符号组成的b位二进制字符串进行操作的错误控制代码执行错误控制。 当存储器单元存储数位r的位时，仅与存储在存储单元中的数据位形成数据符号。 当存储器单元存储少于r的位数时，形成数据符号，其中存储在存储单元中的数据位和具有预定逻辑值的rs位，其中存储在存储单元中的数据位 被布置在数据符号的最低有效部分中，并且具有预定逻辑值的rs位被布置在数据符号的最重要部分中。

公开(公告)号：US20020191444A1

公开(公告)日：2002-12-19

申请号：US10119523

申请日：2002-04-09

Applicant: STMicroelectronics S.r.I.

Inventor： Stefano Gregori ,  Rino Micheloni ,  Andrea Pierin ,  Osama Khouri ,  Guido Torelli

IPC: G11C011/34

CPC classification number: G11C11/5628 ,  G11C16/12

Abstract: A method for programming a nonvolatile memory cell envisages applying in succession, to the gate terminal of the memory cell, a first and a second programming pulse trains with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next in the first programming pulse train is greater than the amplitude increment between one pulse and the next in the second programming pulse train. The programming method envisages applying, to the gate terminal of the memory cell and before the first programming pulse train, a third programming pulse train with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next may be less than the amplitude increment in the first programming pulse train and substantially equal to the amplitude increment in the second programming pulse train, or else may be greater than the amplitude increment in the first programming pulse train.

Abstract translation: 用于编程非易失性存储器单元的方法设想连续地应用到存储器单元的栅极端，第一和第二编程脉冲串，其阶梯形式的脉冲幅度增加，其中在一个脉冲和下一个脉冲之间的振幅增量 第一编程脉冲序列大于第二编程脉冲串中的一个脉冲和下一个脉冲之间的振幅增量。 编程方法设想在存储器单元的栅极端子和第一编程脉冲串之前施加具有阶梯式脉冲幅度增加的第三编程脉冲串，其中，一个脉冲与下一个脉冲之间的振幅增量可能小于 第一编程脉冲序列中的振幅增量基本上等于第二编程脉冲串中的幅度增量，或者可以大于第一编程脉冲序列中的振幅增量。

公开(公告)号：US20020186592A1

公开(公告)日：2002-12-12

申请号：US10118660

申请日：2002-04-08

Applicant: STMicroelectronics S.r.I.

Inventor： Mauro Pagliato ,  Paolo Rolandi ,  Massimo Montanaro

IPC: G11C011/34

CPC classification number: G11C11/5642 ,  G11C11/56 ,  G11C11/5621 ,  G11C2211/5632

Abstract: Described herein is an asynchronous serial dichotomic sense amplifier comprising a first comparator stage having a first input receiving the cell current flowing in the multilevel memory cell, the content of which is to be read, a second input receiving a first reference current, and an output supplying the first of the bits stored in the multilevel memory cell; a multiplexer stage having a selection input connected to the output of the first comparator stage, a first signal input receiving a second reference current, a second signal input receiving a third reference current, and a signal output selectively connectable to the first or the second signal input depending on the logic level present on the selection input; and a second comparator stage having a first input receiving the cell current, a second input connected to the signal output of the multiplexer stage, and an output supplying the second of the bits stored in the multilevel memory cell.

Abstract translation: 这里描述的是一种异步串行二点读出放大器，它包括第一比较器级，该第一比较器级具有接收在多级存储器单元中流动的单元电流的第一输入，其内容将被读取，接收第一参考电流的第二输入和输出 提供存储在多层存储单元中的第一位; 多路复用器级，其具有连接到第一比较器级的输出的选择输入，接收第二参考电流的第一信号输入，接收第三参考电流的第二信号输入和可选地可连接到第一或第二信号的信号 输入取决于选择输入上存在的逻辑电平; 以及第二比较器级，其具有接收单元电流的第一输入，连接到多路复用器级的信号输出的第二输入和提供存储在多电平存储单元中的第二位的输出。

公开(公告)号：US20020159528A1

公开(公告)日：2002-10-31

申请号：US10072818

申请日：2002-02-08

Applicant: STMicroelectronics, S.r.I.

Inventor： Andrea Graziani ,  Luca Celetto ,  Daniele Alfonso ,  Fabrizio Basso ,  Alessandro Cremonesi ,  Danilo Pau

IPC: H04N007/12

CPC classification number: H04N19/40 ,  H04N19/90

Abstract: In order to generate, starting from an input MPEG bitstream, an output MPEG bitstream having at least one entity chosen among syntax, resolution, and bitrate modified with respect to the input bitstream, first portions and second portions are distinguished in the input bitstream, which respectively substantially do not affect and do affect the variation in bitrate. When at least one between the syntax and the resolution is to be modified, the first portions of the input bitstream are subjected to the required translation, then transferring said first portions subjected to syntax and/or resolution translation to the output bitstream. When the resolution is left unaltered, the second portions are transferred from the input bitstream to the output bitstream in the substantial absence of processing operations. When the resolution is changed, the second portions of the input bitstream are subjected to a filtering in the domain of the discrete cosine transform.

Abstract translation: 为了从输入MPEG比特流开始，输出MPEG比特流，其具有相对于输入比特流修改的语法，分辨率和比特率中选择的至少一个实体，在输入比特流中区分第一部分和第二部分，其中 分别基本上不影响并确实影响比特率的变化。 当要修改语法和分辨率之间的至少一个时，输入比特流的第一部分经受所需的翻译，然后将经过语法和/或分辨率转换的所述第一部分传送到输出比特流。 当分辨率保持不变时，在实质上没有处理操作的情况下，第二部分从输入比特流传送到输出比特流。 当分辨率改变时，输入比特流的第二部分在离散余弦变换的域中进行滤波。