公开(公告)号：US20140332860A1

公开(公告)日：2014-11-13

申请号：US13890849

申请日：2013-05-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/8256 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1606 ,  H01L29/41725 ,  H01L29/66045 ,  H01L29/6656 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/78645

Abstract: Methods and systems for forming stacked transistors. Such methods include forming a lower channel layer on a substrate; forming a pair of vertically aligned gate regions over the lower channel layer; forming a pair of vertically aligned source regions and a pair of vertically aligned drain regions on the lower channel material, each pair separated by an insulator; forming an upper channel material over the source regions, drain regions, and gate regions; and providing electrical access to the source, drain, and gate regions.

Abstract translation: 用于形成堆叠晶体管的方法和系统。 这种方法包括在基底上形成下通道层; 在所述下通道层上形成一对垂直对准的栅极区; 在下通道材料上形成一对垂直排列的源极区域和一对垂直排列的漏极区域，每对漏极区域由绝缘体隔开; 在源极区域，漏极区域和栅极区域上形成上部沟道材料; 并提供对源极，漏极和栅极区域的电接入。

公开(公告)号：US08809860B2

公开(公告)日：2014-08-19

申请号：US13775968

申请日：2013-02-25

Applicant: International Business Machines Corporation

Inventor： Kuen-Ting Shiu ,  Dechao Guo ,  Shu-Jen Han ,  Edward W. Kiewra ,  Masaharu Kobayashi

IPC: H01L29/04 ,  H01L29/10

CPC classification number: H01L29/0603 ,  H01L21/28158 ,  H01L21/28264 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/78 ,  H01L29/7833

Abstract: The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure.

Abstract translation: 本公开通过在单晶III-V化合物半导体材料层的上表面上提供薄的晶体中间层来减少并且在一些情况下消除III-V族化合物半导体材料中的界面态的密度，以保护单晶III-V化合物半导体材料层的结晶度 单晶III-V化合物半导体材料层的表面原子在进一步处理结构之前。

公开(公告)号：US08766345B2

公开(公告)日：2014-07-01

申请号：US13690593

申请日：2012-11-30

Applicant: International Business Machines Corporation

Inventor： Damon B. Farmer ,  Aaron D. Franklin ,  Shu-Jen Han ,  George S. Tulevski

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L28/40 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01G4/008 ,  H01G4/33 ,  H01L28/90

Abstract: An on-chip decoupling capacitor is disclosed. One or more carbon nanotubes are coupled to a first electrode of the capacitor. A dielectric skin is formed on the one or more carbon nanotubes. A metal coating is formed on the dielectric skin. The dielectric skin is configured to electrically isolate the one or more carbon nanotubes from the metal coating.

公开(公告)号：US20140154858A1

公开(公告)日：2014-06-05

申请号：US13970081

申请日：2013-08-19

Applicant: International Business Machines Corporation

Inventor： Damon B. Farmer ,  Aaron D. Franklin ,  Shu-Jen Han ,  George S. Tulevski

IPC: H01L49/02

CPC classification number: H01L28/40 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01G4/008 ,  H01G4/33 ,  H01L28/90

Abstract: An on-chip decoupling capacitor is disclosed. One or more carbon nanotubes are coupled to a first electrode of the capacitor. A dielectric skin is formed on the one or more carbon nanotubes. A metal coating is formed on the dielectric skin. The dielectric skin is configured to electrically isolate the one or more carbon nanotubes from the metal coating.

公开(公告)号：US20140151847A1

公开(公告)日：2014-06-05

申请号：US13690593

申请日：2012-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Damon B. Farmer ,  Aaron D. Franklin ,  Shu-Jen Han ,  George S. Tulevski

IPC: H01L49/02

CPC classification number: H01L28/40 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01G4/008 ,  H01G4/33 ,  H01L28/90

Abstract: An on-chip decoupling capacitor is disclosed. One or more carbon nanotubes are coupled to a first electrode of the capacitor. A dielectric skin is formed on the one or more carbon nanotubes. A metal coating is formed on the dielectric skin. The dielectric skin is configured to electrically isolate the one or more carbon nanotubes from the metal coating.

Abstract translation: 公开了片上去耦电容器。 一个或多个碳纳米管被耦合到电容器的第一电极。 在一个或多个碳纳米管上形成电介质皮肤。 在电介质皮肤上形成金属涂层。 电介质皮肤被配置为将一种或多种碳纳米管与金属涂层电隔离。

公开(公告)号：US20140151641A1

公开(公告)日：2014-06-05

申请号：US13705845

申请日：2012-12-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shu-Jen Han ,  Alberto Valdes Garcia

IPC: H01L29/66 ,  H01L29/775

CPC classification number: H01L29/16 ,  B82Y30/00 ,  H01L21/8221 ,  H01L29/1606 ,  H01L29/66045 ,  H01L29/778 ,  H01L2224/05568 ,  H01L2224/13023

Abstract: Three-dimensional integrated circuits and method for fabricating the same include forming one or more passive components in a passive-layer dielectric; depositing additional dielectric material on the passive-layer dielectric; forming a gate structure in the additional dielectric material; forming a gate dielectric layer on the gate structure and the additional dielectric material; forming a thin channel material on the gate dielectric; forming source and drain regions in electrical contact with the thin channel material to form a transistor; and passivating the transistor and providing electrical access to the source and drain regions.

Abstract translation: 三维集成电路及其制造方法包括在无源层电介质中形成一个或多个无源部件; 在无源层电介质上沉积额外的介电材料; 在所述附加电介质材料中形成栅极结构; 在栅极结构和附加电介质材料上形成栅极电介质层; 在栅极电介质上形成薄沟道材料; 形成与所述薄沟道材料电接触以形成晶体管的源区和漏区; 并钝化晶体管并提供对源区和漏区的电接入。

公开(公告)号：US20130328016A1

公开(公告)日：2013-12-12

申请号：US13966427

申请日：2013-08-14

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

IPC: G01N27/414

CPC classification number: G01N27/4145 ,  G01N27/4146 ,  H01L29/1606 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0048

Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.

公开(公告)号：US20130230978A1

公开(公告)日：2013-09-05

申请号：US13859284

申请日：2013-04-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dechao Guo ,  Wilfried E.A. Haensch ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC: H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/66507 ,  H01L29/66545

Abstract: A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer.

Abstract translation: 提供了一种形成具有自对准接触的栅极结构的方法，并且包括将牺牲层和次级层顺序地沉积到设置在栅极结构的位置处的多晶硅上，封装牺牲层，第二层和聚 -Si，通过形成在次级层中的开口去除牺牲层，并在至少由牺牲层正式占据的空间内形成硅化物。

公开(公告)号：US20130168834A1

公开(公告)日：2013-07-04

申请号：US13775968

申请日：2013-02-25

Applicant: International Business Machines Corporation

Inventor： Kuen-Ting Shiu ,  Dechao Guo ,  Shu-Jen Han ,  Edward W. Kiewra ,  Masaharu Kobayashi

IPC: H01L29/06

CPC classification number: H01L29/0603 ,  H01L21/28158 ,  H01L21/28264 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/78 ,  H01L29/7833

Abstract: The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure.

Abstract translation: 本公开通过在单晶III-V化合物半导体材料层的上表面上提供薄的晶体中间层来减少并且在一些情况下消除III-V族化合物半导体材料中的界面态的密度，以保护单晶III-V化合物半导体材料层的结晶度 单晶III-V化合物半导体材料层的表面原子在进一步处理结构之前。