公开(公告)号：US20230136202A1

公开(公告)日：2023-05-04

申请号：US17720238

申请日：2022-04-13

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Angela S. Parekh

IPC: H01L23/373 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/367

Abstract: A semiconductor device assembly is provided. The assembly includes a first semiconductor device including a plurality of electrical contacts on an upper surface thereof; a monolithic silicon structure having a lower surface in contact with the upper surface of the first semiconductor device, the monolithic silicon structure including a cavity extending from the lower surface completely through a body of the monolithic silicon structure to a top surface of the monolithic silicon structure; and a second semiconductor device disposed in the cavity, the second semiconductor device including a plurality of interconnects, each operatively coupled to a corresponding one of the plurality of electrical contacts.

公开(公告)号：US11631684B2

公开(公告)日：2023-04-18

申请号：US17229672

申请日：2021-04-13

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/308 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768 ,  H01L27/112 ,  H01L21/67 ,  H01L21/3215 ,  H01L27/11553

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11587919B2

公开(公告)日：2023-02-21

申请号：US16932098

申请日：2020-07-17

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip ,  Kunal R. Parekh ,  Akira Goda

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises first control logic region comprising a first control logic devices including at least a word line driver. The microelectronic device further comprise a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20230051126A1

公开(公告)日：2023-02-16

申请号：US17885325

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Aliasger T. Zaidy ,  Sean S. Eilert ,  Glen E. Hush ,  Kunal R. Parekh

IPC: G11C11/4093 ,  G11C11/4096 ,  G06F3/06 ,  G06F13/16

Abstract: A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data.

公开(公告)号：US20230050961A1

公开(公告)日：2023-02-16

申请号：US17885242

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Kunal R. Parekh ,  Aliasger T. Zaidy ,  Glen E. Hush

IPC: G16B50/10 ,  H01L25/18 ,  G11C11/4093 ,  G11C11/4096 ,  G16B30/00 ,  G06F13/28

Abstract: A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of a genetic sequence from the memory die and through a wafer-on-wafer bond. The logic die can also perform a genome annotation lotic operation to attach biological information to the genetic sequence. An annotated genetic sequence can be provided as an output.

公开(公告)号：US11557569B2

公开(公告)日：2023-01-17

申请号：US16905747

申请日：2020-06-18

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L29/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L49/02

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive structure comprising a first portion overlying the base structure and second portions vertically extending from the first portion and into the base structure, a stack structure overlying the doped semiconductive structure, cell pillar structures vertically extending through the stack structure and to the doped semiconductive structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The carrier structure and the second portions of the doped semiconductive structure are removed. The first portion of the doped semiconductive structure is then patterned to form at least one source structure coupled to the cell pillar structures. Devices and systems are also described.

公开(公告)号：US20230005903A1

公开(公告)日：2023-01-05

申请号：US17364476

申请日：2021-06-30

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Kunal R. Parekh

IPC: H01L25/18 ,  H01L27/108 ,  H01L25/00 ,  H01L23/00

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, contact structures coupled to the digit lines, word lines coupled to the memory cells, additional contact structures coupled to the word lines, and isolation material surrounding the contact structures and the additional contact structures and overlying the memory cells. An additional microelectronic device structure assembly is formed and comprises control logic devices, further contact structures coupled to the control logic devices, and additional isolation material surrounding the further contact structures and overlying the control logic devices. The additional microelectronic device structure assembly is attached to the microelectronic device structure assembly by bonding the additional isolation material to the isolation material and by bonding the further contact structures to the contact structures and the additional contact structures. Microelectronic devices and electronic systems are also described.

公开(公告)号：US11527436B2

公开(公告)日：2022-12-13

申请号：US16902115

申请日：2020-06-15

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh ,  Sarah A. Niroumand

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/306 ,  H01L21/311

Abstract: Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.

公开(公告)号：US11482538B2

公开(公告)日：2022-10-25

申请号：US17062222

申请日：2020-10-02

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kunal R. Parekh

IPC: H01L21/00 ,  H01L27/11582 ,  H01L29/47 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11529 ,  H01L21/285

Abstract: A microelectronic device comprises a stack structure, cell pillar structures, an active body structure, digit line structures, and control logic devices. The stack structure comprises vertically neighboring tiers, each of the vertically neighboring tiers comprising a conductive structure and an insulative structure vertically neighboring the conductive structure. The cell pillar structures vertically extend through the stack structure and each comprise a channel material and an outer material stack horizontally interposed between the channel material and the stack structure. The active body structure vertically overlies the stack structure and is in contact with the channel material of the cell pillar structures. The active body structure comprises a metal material having a work function greater than or equal to about 4.7 electronvolts. The digit line structures vertically underlie the stack structure and are coupled to the cell pillar structures. Memory devices, electronic systems, and methods of forming a microelectronic device are also described.

公开(公告)号：US20220149015A1

公开(公告)日：2022-05-12

申请号：US17649022

申请日：2022-01-26

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Paolo Tessariol ,  Akira Goda

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768 ,  H01L23/482

Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.