公开(公告)号：US20220115368A1

公开(公告)日：2022-04-14

申请号：US17067033

申请日：2020-10-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Kaustubh Shanbhag ,  Glenn Workman

IPC: H01L27/02 ,  H01L21/762 ,  H01L21/8238

Abstract: The disclosure provides integrated circuit (IC) structures and methods to form the same. Methods according to the disclosure may be performed on a substrate having a first doping type, the substrate extending between a first end and a second end. A deep well is formed within the substrate, the deep well including a well boundary defined between the deep well and a remainder of the substrate. The well boundary is horizontally distal to a midpoint between the first end and the second end of the substrate. A first active semiconductor region is formed at least partially over the substrate, and an oppositely-doped second active semiconductor region is formed at least partially over the deep well.

公开(公告)号：US20220115329A1

公开(公告)日：2022-04-14

申请号：US17070377

申请日：2020-10-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Johnatan A. KANTAROVSKY ,  Vibhor JAIN ,  Siva P. ADUSUMILLI ,  Ajay RAMAN ,  Sebastian T. VENTRONE ,  Yves T. NGU

IPC: H01L23/552 ,  H01L23/00 ,  H01L49/02 ,  H01L23/522

Abstract: The present disclosure relates to integrated circuits, and more particularly, to an anti-tamper x-ray blocking package for secure integrated circuits and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: one or more devices on a front side of a semiconductor material; a plurality of patterned metal layers under the one or more devices, located and structured to protect the one or more devices from an active intrusion; an insulator layer between the plurality of patterned metal layers; and at least one contact providing an electrical connection through the semiconductor material to a front side of the plurality of metals.

公开(公告)号：US11266940B2

公开(公告)日：2022-03-08

申请号：US16427500

申请日：2019-05-31

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Charles Vreugde ,  Robert Baldino

IPC: B01D46/00 ,  B01D46/02 ,  B01D46/10 ,  B01D46/52

Abstract: One illustrative system disclosed herein includes an upper filter, a lower filter positioned vertically below the upper filter, at least one incoming air inlet positioned vertically above the upper filter, and a vacuum pump positioned vertically below the lower filter, the vacuum pump including an outlet, wherein an incoming air stream is adapted to flow downwardly through the at least one incoming air inlet, then through the upper filter, then through the lower filter and then out of the outlet of the vacuum pump where it exits as a cleaned air stream.

公开(公告)号：US20220069125A1

公开(公告)日：2022-03-03

申请号：US17454481

申请日：2021-11-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： IGNASI CORTES ,  ALBAN ZAKA ,  TOM HERRMANN ,  EL MEHDI BAZIZI ,  RICHARD FRANCIS TAYLOR, III

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66

Abstract: The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.

公开(公告)号：US20220068340A1

公开(公告)日：2022-03-03

申请号：US17007512

申请日：2020-08-31

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Bipul C. Paul ,  Steven R. Soss

IPC: G11C11/16 ,  G11C7/20 ,  G11C5/06

Abstract: Disclosed are embodiments of a non-volatile static random access memory (NV-SRAM) cell. The NV-SRAM cell includes a static random access memory (SRAM) circuit (e.g., a conventional high performance, high reliability SRAM circuit). However, in order to avoid volatility while still retaining the advantages associated with SRAM circuit operation, the NV-SRAM cell also includes a pair of NVM circuits. These NVM circuits capture data values stored on the data nodes of the SRAM circuit prior to power down and rewrite those data values back onto the data nodes of the SRAM circuit upon power up. Also disclosed are embodiments of a method of operating a selected NV-SRAM cell in a memory array.

公开(公告)号：US11264504B2

公开(公告)日：2022-03-01

申请号：US16751779

申请日：2020-01-24

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Yanping Shen ,  Haiting Wang ,  Hong Yu

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/423

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a scheme of active and dummy fin structures and methods of manufacture. The structure includes: an active fin structure; at least one dummy fin structure running along at least one side of the active fin structure along its length; a fin cut separating the at least one dummy fin structure along its longitudinal axes; and a gate structure extending over the active fin structure and the fin cut.

公开(公告)号：US11264382B2

公开(公告)日：2022-03-01

申请号：US16942816

申请日：2020-07-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jiehui Shu ,  Bharat V. Krishnan

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8234

Abstract: Disclosed are a method of forming a fin-type field effect transistor (FINFET) and a FINFET structure. In the method, isolation regions are formed on opposing sides of a semiconductor fin. Each isolation region is shorter than the fin, has a lower isolation portion adjacent to a lower fin portion, and has an upper isolation portion that is narrower than the lower isolation portion and separated from a bottom section of an upper fin portion by a space. Surface oxidation of the upper fin portion thins the top section, but leaves the bottom section relatively wide. During gate formation, the gate dielectric layer fills the spaces between the bottom section of the upper fin portion and the adjacent isolation regions. Thus, the gate conductor layer is formed above any fin bulge area and degradation of gate control over the channel region due to a non-uniform fin width is minimized or avoided.

公开(公告)号：US11248822B2

公开(公告)日：2022-02-15

申请号：US16522270

申请日：2019-07-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Thomas Huang

IPC: H01L21/67 ,  F24H1/00

Abstract: One illustrative energy recovery system disclosed herein includes a semiconductor fabrication facility (“fab”) and a closed chilled water loop including a chilled water stream delivered to the fab and a returning water stream that is received from the fab. In this example, the system also includes a primary heat exchanger having a first fluid side and a second fluid side, the first fluid side is adapted to receive supply water and the second fluid side is adapted to receive at least a portion of the returning return water stream, wherein the primary heat exchanger is adapted to effectuate heat transfer between the supply water flowing in the first fluid side and the returning water stream flowing in the second fluid side.

公开(公告)号：US11239336B2

公开(公告)日：2022-02-01

申请号：US16788922

申请日：2020-02-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Wei Hong ,  Yanping Shen ,  Domingo A. Ferrer ,  Hong Yu

IPC: H01L29/45 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L27/088 ,  H01L29/165 ,  H01L29/78 ,  H01L21/285

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a niobium-based silicide layer. An IC structure according to the disclosure includes a transistor on a substrate, the transistor including a gate structure above the substrate and a source/drain (S/D) region on the substrate adjacent the gate structure. A niobium-based silicide layer is on at least an upper surface the S/D region of the transistor, and extends across substantially an entire width of the S/D region. An S/D contact to the S/D region is in contact with the niobium-based silicide layer.

公开(公告)号：US11239087B2

公开(公告)日：2022-02-01

申请号：US16662091

申请日：2019-10-24

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Heng Yang ,  David C. Pritchard ,  George J. Kluth ,  Anurag Mittal ,  Hongru Ren ,  Manjunatha G. Prabhu ,  Kai Sun ,  Neha Nayyar ,  Lixia Lei

IPC: H01L27/12 ,  H01L21/308 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L21/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.