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231.发明申请公开(公告)号：US20190146868A1
公开(公告)日：2019-05-16
申请号：US15810731
申请日：2017-11-13
Applicant: STMicroelectronics International N.V. , STMicroelectronics S.r.l. , STMicroelectronics (Crolles 2) SAS
Inventor： Om Ranjan , Riccardo Gemelli , Denis Dutey
Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.
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公开(公告)号：US10263603B2
公开(公告)日：2019-04-16
申请号：US15462494
申请日：2017-03-17
Inventor： Pascal Urard , Alok Kumar Tripathi
IPC: H03K3/012 , H03K3/356 , H03K19/00 , H03K3/0233 , H03K3/3562
Abstract: The synchronous retention flip-flop circuit comprises a first circuit module suitable for being powered by an interruptible power source and a second circuit module suitable for being powered by a permanent power source. The first circuit module includes first and second latch stages, which are configured to store at least one datum while said interruptible power source is supplying power, transmitting means suitable for being controlled by a second control signal and configured to deliver said at least one datum to the second circuit module before an interruption of said interruptible power source, the second circuit module being configured to preserve said at least one datum during said interruption, and restoring means suitable for being controlled by a first control signal and configured to restore said at least one datum at the end of said interruption. Only the second control signal remains active during interruption of the interruptible power source.
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公开(公告)号：US10250133B2
公开(公告)日：2019-04-02
申请号：US15652447
申请日：2017-07-18
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana
Abstract: A single stage voltage quadrupler circuit includes a first capacitive voltage boosting circuit responsive to a first clock signal and operable to boost a voltage at a first node in response to the first clock signal from a first voltage level to a second voltage level that is substantially two times the first voltage level. A pass transistor selectively passes the boosted voltage at the first node to a second node in response to a control signal generated by a bootstrapping capacitor circuit in response to the level shifted first clock signal. A second capacitive boosting circuit is operable to boost the voltage at the second node in response to a level shifted second clock signal that is the logical invert of the level shifted first clock signal to third voltage level that is substantially four times the first voltage level.
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234.发明申请公开(公告)号：US20190097641A1
公开(公告)日：2019-03-28
申请号：US15718715
申请日：2017-09-28
Applicant: STMicroelectronics International N.V.
Inventor： Nitin Gupta , Ankit Gupta , Anand Kumar
Abstract: Disclosed herein is a method of calibrating a voltage controlled oscillator (VCO) for a phase locked loop. The method includes prior to activating the phase locked loop, and prior to activating a frequency locked loop, causing a bias signal generator circuit to generate a control signal with a fixed control voltage for the VCO. The method continued with activating the frequency locked loop, and adjusting the bias signal generator to calibrate a transconductance of the bias signal generator while the frequency locked loop is activated. The frequency locked loop is then deactivated, and the phase locked loop is activated.
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公开(公告)号：US10242303B2
公开(公告)日：2019-03-26
申请号：US15473295
申请日：2017-03-29
Applicant: STMicroelectronics International N.V.
Inventor： Vinko Kunc , Iztok Bratuz , Albin Pevec , Kosta Kovacic , Maksimiljan Stiglic
IPC: G06K19/07 , G06K19/077 , H04L7/033
Abstract: In an embodiment, a carrier signal generation circuit can be used for a Radio-frequency identification (RFID) transponder device. A frequency divider circuit has a first input to receive a first frequency signal, a second input to receive a division ratio signal, and an output to provide a carrier signal as a function of the first frequency signal and the division ratio signal. A phase difference circuit has a first input to receive an analog reader device carrier signal, a second input to receive a signal based on the first frequency signal and an output to provide a digital phase difference signal as a function of the reader device carrier signal and the signal based on the first frequency signal. A signal processor has an input coupled to the output of the phase difference circuit.
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Patent Agency Ranking
公开(公告)号：US10222819B2
公开(公告)日：2019-03-05
申请号：US15866651
申请日：2018-01-10
Applicant: STMicroelectronics International N.V.
Inventor： Abhirup Lahiri
Abstract: A reference voltage generator circuit includes a circuit that generates a complementary to absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) current. An output current circuit generates, from the PTAT current, a sink PTAT current sunk from a first node and a source PTAT current sourced to a second node, wherein the sink and source PTAT currents are equal. A resistor is directly connected between the first node and the second node. A divider circuit divides the CTAT voltage to generate a divided CTAT voltage applied to the first node. A voltage at the second node is a fractional bandgap reference voltage equal to a sum of the divided CTAT voltage and a voltage drop across the resistor that is proportional to a resistor current equal to the sink and source PTAT currents.
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公开(公告)号：US10222415B2
公开(公告)日：2019-03-05
申请号：US15375542
申请日：2016-12-12
Applicant: STMicroelectronics International N.V.
Inventor： Tejinder Kumar , Suchi Prabhu Tandel , Rakesh Malik
IPC: G01R31/317 , G01R31/3193
Abstract: Disclosed herein is a test circuit for testing a device under test (DUT). The test circuit receives a test pattern output by the DUT. A content addressable memory (CAM) stores expected test data at a plurality of address locations, receives the test pattern, and outputs an address of the CAM containing expected test data matching the received test pattern. A memory also stores the expected test data at address locations corresponding to the address locations of the CAM. A control circuit causes the memory to output the expected test data stored therein at the address output by the CAM. Comparison circuitry receives the test pattern from the input, and compares that received test pattern to the expected test data output by the control circuit, and generates an error count as a function of a number of bit mismatches between the received test pattern and the expected test data.
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公开(公告)号：US20190064271A1
公开(公告)日：2019-02-28
申请号：US15684334
申请日：2017-08-23
Applicant: STMicroelectronics International N.V.
Inventor： Venkata Narayanan Srinivasan , Manish Sharma
IPC: G01R31/3185 , G01R31/317
CPC classification number: G01R31/31705 , G01R31/318597
Abstract: A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.
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公开(公告)号：US10186022B2
公开(公告)日：2019-01-22
申请号：US15636294
申请日：2017-06-28
Inventor： Mahesh Chandra , Antoine Drouot
Abstract: Various embodiments provide an optimized image filter. The optimized image and video obtains an input image and selects a target pixel for modification. Difference values are then determined between the selected target pixel and each reference pixel of a search area. Subsequently, a weighting function is used to determine weight values for each of the reference pixels of the search area based on their respective difference value. The selected target pixel is then modified by the optimized image filter using the determined weight values. A new target pixel in an apply patch is then selected for modification. The new target pixel is modified using the previously determined weight values reassigned to a new set of reference pixels. The previously determined weight values are reassigned to the new set of reference pixels based on each of the new set of reference pixels' position relative to the new target pixel.
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公开(公告)号：US10176869B2
公开(公告)日：2019-01-08
申请号：US16044280
申请日：2018-07-24
Inventor： Marco Pasotti , Marcella Carissimi , Vikas Rana
Abstract: A method is provided for operating a memory device that includes an array of memory cells coupled to a plurality of bitlines. A memory cell is selected from among the array of memory cells. The selected memory cell is coupled to a selected bitline. During a program operation, a program current pulse is injected into the selected memory cell via a first switch coupled to the bitline. At an end of the program current pulse, the selected bitline is discharged via a second switch coupled to the bitline.
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