公开(公告)号：US20210073450A1

公开(公告)日：2021-03-11

申请号：US17094743

申请日：2020-11-10

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Thomas BOESCH ,  Giuseppe DESOLI

IPC: G06F30/327 ,  G06N3/04 ,  G06N3/08 ,  G06F30/34 ,  G06N3/063 ,  G06F9/445 ,  G06F13/40 ,  G06F15/78

Abstract: Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs. The input port architectural composition is defined by a plurality of M data paths including A data inputs and B control inputs.

公开(公告)号：US10930650B2

公开(公告)日：2021-02-23

申请号：US16450141

申请日：2019-06-24

Applicant: STMicroelectronics International N.V.

Inventor： Vishal Kumar Sharma

IPC: H01L27/092 ,  H01L27/02 ,  H01L29/06

Abstract: In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures.

公开(公告)号：US20210006237A1

公开(公告)日：2021-01-07

申请号：US16460191

申请日：2019-07-02

Applicant: STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal

IPC: H03K3/037 ,  H03L7/00 ,  H03K19/21

Abstract: A synchronizer circuit includes a first synchronizer having a first input for receiving a signal associated with a first clock signal, a second input for receiving a second clock signal, and an output for providing a synchronizer circuit output signal; a second synchronizer having a first input for receiving the signal associated with the first clock signal, a second input for receiving the second clock signal, and an output; a detection stage having a first input coupled to the output of the first synchronizer and to the output of the second synchronizer, a second input for receiving the second clock signal, and an output; and a fault output stage having a first input coupled to the detection stage, a second input for receiving the second clock signal, and an output for providing a fault output signal.

公开(公告)号：US10862487B2

公开(公告)日：2020-12-08

申请号：US16674207

申请日：2019-11-05

Applicant: STMicroelectronics International N.V.

Inventor： Anand Kumar ,  Nitin Gupta ,  Nitin Jain

IPC: H03L1/00 ,  H03L7/183 ,  H03L7/087 ,  H03L7/085

Abstract: A circuit includes a frequency detector generating a comparison signal as a function of a comparison between a reference signal and a feedback signal. An oscillator generates an output signal as a function of the comparison signal. A frequency divider, in operation, divides the output signal by a division value to produce the feedback signal as having a frequency that is a multiple of a frequency of the reference signal. A frequency counter circuit measures the frequency of the reference signal and generates a count signal based thereupon. A control circuit adjusts the division value used by the frequency divider, in operation, based upon the count signal.

公开(公告)号：US10855912B2

公开(公告)日：2020-12-01

申请号：US16030572

申请日：2018-07-09

Applicant: STMicroelectronics International N.V.

Inventor： Rosarium Pila

IPC: H04N5/232 ,  H04N1/21 ,  H04N5/235

Abstract: A method and apparatus for capturing stable images are disclosed. An ambient light sensor makes measurements of ambient light. A change in ambient light between two measurements is determined. If the change in ambient light measurements falls in a predefined range, then the change may be attributable to ambient light sensor being blocked by a user to trigger image capturing. Consequently, a camera is triggered to capture an image. Conversely, if the change in ambient light measurement is outside the range, image capturing is not triggered as the change may be attributable to other factors.

公开(公告)号：US20200343869A1

公开(公告)日：2020-10-29

申请号：US16829088

申请日：2020-03-25

Applicant: STMicroelectronics International N.V.

Inventor： Nitin GUPTA ,  Prashutosh GUPTA

IPC: H03F3/45 ,  H03G1/00 ,  H03F1/22 ,  H03F1/32

Abstract: A differential pair of transistors receives input voltages. Current mirror transistors and cascode transistors are coupled to the differential pair of transistors. The differential pair of transistors is coupled between the cascode transistors and a tail transistor that draws a first bias current from a tail node, the first bias current having a magnitude equal to a product of a total bias current and a constant that is less than one. A first current source transistor draws a second bias current from a node between the differential pair and cascode transistors so the second bias current bypasses one transistor of the differential pair of transistors. The second bias current has a magnitude equal to a product of the total bias current and a value equal to one minus the constant. An output stage is biased by an output at node between the cascode transistors and the current mirror transistors.

公开(公告)号：US20200342940A1

公开(公告)日：2020-10-29

申请号：US16846938

申请日：2020-04-13

Applicant: STMicroelectronics International N.V.

Inventor： Tanmoy ROY ,  Tanuj KUMAR ,  Shishir KUMAR

IPC: G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  G11C29/44

Abstract: First and second memory arrays have common word lines driven by a row decoder in response to a row address. A first word line encoder associated with the first memory array encodes signals on the word lines to generate a first encoded value, and a second word line encoder associated with the second memory array encodes signals on the word lines to generate a second encoded value. Comparison circuitry compares the first encoded value to a first expected value (e.g., a first portion of the row address) and compares the second encoded value to a second expected value (e.g., a second portion of the row address). An error flag is asserted to indicate presence of a word line fault based upon a lack of match between the first encoded value and the first expected value and/or a lack of match between the second encoded value and the second expected value.

公开(公告)号：US10795389B2

公开(公告)日：2020-10-06

申请号：US16217872

申请日：2018-12-12

Applicant: STMicroelectronics International N.V.

Inventor： Kapil Kumar Tyagi ,  Nitin Gupta

IPC: G05F1/46 ,  G05F1/613 ,  G05F1/575 ,  G05F1/56

Abstract: An electronic device including a low dropout regulator having an output coupled to a first conduction terminal of a transistor, with a second conduction terminal of the transistor being coupled to an output node of the electronic device. A method for operating the device to switch into a power on mode includes: turning on the low dropout regulator, removing a DC bias from the second conduction terminal of the transistor, and turning on the transistor. A method for operating the device to switch into a power down mode includes: turning off the transistor, forming the DC bias at the second conduction terminal of the transistor, and turning off the low dropout regulator.

公开(公告)号：US20200313708A1

公开(公告)日：2020-10-01

申请号：US16825887

申请日：2020-03-20

Applicant: STMicroelectronics International N.V.

Inventor： Gagan Midha

IPC: H04B1/12

Abstract: An automatic gain controller for a receiver analog frontend is provided. The automatic gain controller sets a plurality of gains for a plurality of analog frontend stages, respectively. The automatic gain controller detects a first signal level at an output of the analog frontend, determines that the first signal level is saturated and sets a first gain of a first analog frontend stage of the plurality of analog frontend stages to a first coarse gain value based on the first signal level. In response to setting the first gain, the automatic gain controller detects a second signal level at the output of the analog frontend, determines whether the second signal level is saturated and on a condition that the second signal level is not saturated, sets the first gain of the first analog frontend stage to a first fine gain value based on the second signal level.

公开(公告)号：US20200274504A1

公开(公告)日：2020-08-27

申请号：US16746518

申请日：2020-01-17

Applicant: STMicroelectronics International N.V.

Inventor： Prashant Singh

IPC: H03F3/45

Abstract: A squelch detection device is provided. The squelch detection device receives first and second input signals and first and second threshold voltages. The squelch detection device determines a first common mode of the first and second input signals and a second common mode of the first and second threshold voltages. The squelch detection device averages the first common mode with the second common mode to produce an average common mode and sets the first common mode of the first and second input signals to the average common mode. The squelch detection device sets the second common mode of the first and second threshold voltages to the average common mode and determines a state of a squelch signal, indicative of whether the first and second input signals are attributable to noise, based on the first and second input signals and the first and second threshold voltages.