公开(公告)号：US20240387676A1

公开(公告)日：2024-11-21

申请号：US18785512

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG

IPC: H01L29/49 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: A device comprises a substrate, a semiconductor channel over the substrate, and a gate structure over and laterally surrounding the semiconductor channel. The gate structure comprises a first dielectric layer comprising a first dielectric material including dopants. A second dielectric layer is on the first dielectric layer, and comprises a second dielectric material substantially free of the dopants. A metal fill layer is over the second dielectric layer.

公开(公告)号：US20240387658A1

公开(公告)日：2024-11-21

申请号：US18783869

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/285 ,  H01L21/321 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/535 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure includes a metal gate structure (MG) formed over a substrate, a first gate spacer formed on a first sidewall of the MG, a second gate spacer formed on a second sidewall of the MG opposite to the first sidewall, where the second gate spacer is shorter than the first gate spacer, a source/drain (S/D) contact (MD) adjacent to the MG, where a sidewall of the MD is defined by the second gate spacer, and a contact feature configured to electrically connect the MG to the MD.

公开(公告)号：US20240387651A1

公开(公告)日：2024-11-21

申请号：US18320480

申请日：2023-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Chih WANG ,  Yu-Tien SHEN ,  Yu-Chen CHANG

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region; and a second transistor above the first transistor in a vertical direction, and having a second source/drain region, the second transistor being offset from the first transistor in a first direction that is perpendicular to the vertical direction; a first source/drain contact electrically coupled to the first source/drain region; a second source/drain contact electrically coupled to the second source/drain region; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact, and including an oblique portion that extends from the first source/drain contact to the second source/drain contact at an offset angle from the vertical direction.

公开(公告)号：US20240387629A1

公开(公告)日：2024-11-21

申请号：US18786808

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Min Liu ,  Li-Li Su ,  Chii-Horng Li ,  Yee-Chia Yeo

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786

Abstract: A device includes a first nanostructure over a semiconductor substrate; a second nanostructure over the first nanostructure; a gate structure surrounding the first nanostructure and the second nanostructure; a first epitaxial region in the semiconductor substrate adjacent the gate structure, wherein the first epitaxial region is a first doped semiconductor material; and a second epitaxial region over the first epitaxial region, wherein the second epitaxial region is adjacent the first nanostructure and the second nanostructure, wherein the second epitaxial region is a second doped semiconductor material that is different from the first doped semiconductor material. In an embodiment, the first doped semiconductor material has a smaller doping concentration than the second doped semiconductor material.

公开(公告)号：US20240387628A1

公开(公告)日：2024-11-21

申请号：US18786532

申请日：2024-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Jia-Ni Yu ,  Chun-Fu Lu ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a first channel region in a first region and over a second channel region in a second region; introducing a first dipole element into the first dielectric layer in the first region to form a first dipole-containing gate dielectric layer in the first region; forming a second dielectric layer over the first dipole-containing gate dielectric layer; introducing fluorine into the second dielectric layer to form a first fluorine-containing gate dielectric layer over the first dipole-containing gate dielectric layer; and forming a gate electrode over the first fluorine-containing gate dielectric layer.

公开(公告)号：US20240387574A1

公开(公告)日：2024-11-21

申请号：US18786821

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Lin CHEN ,  Chun-Hao CHOU ,  Kuo-Cheng LEE

IPC: H01L27/146

Abstract: Implementations described herein reduce electron-hole pair generation due to silicon dangling bonds in pixel sensors. In some implementations, the silicon dangling bonds in a pixel sensor may be passivated by silicon-fluorine (Si—F) bonding in various portions of the pixel sensor such as a transfer gate contact via or a shallow trench isolation region, among other examples. The silicon-fluorine bonds are formed by fluorine implantation and/or another type of semiconductor processing operation. In some implementations, the silicon-fluorine bonds are formed as part of a cleaning operation using fluorine (F) such that the fluorine may bond with the silicon of the pixel sensor. Additionally, or alternatively, the silicon-fluorine bonds are formed as part of a doping operation in which boron (B) and/or another p-type doping element is used with fluorine such that the fluorine may bond with the silicon of the pixel sensor.

公开(公告)号：US20240387550A1

公开(公告)日：2024-11-21

申请号：US18788583

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Chih-Hao Wang ,  Shi Ning Ju ,  Jia-Chuan You ,  Kuo-Cheng Chiang

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes providing a structure having two fins extending from a substrate; an isolation structure isolating bottom portions of the fins; source/drain (S/D) features over each of the fins; a dielectric fin oriented lengthwise parallel to the fins and disposed between the two fins and over the isolation structure; a dummy gate stack over the isolation structure, the fins, and the dielectric fin; and one or more dielectric layers over sidewalls of the dummy gate stack. The method further includes removing the dummy gate stack to result in a gate trench within the one or more dielectric layers, wherein the dielectric fin is exposed in the gate trench; trimming the dielectric fin to reduce a width of the dielectric fin; and after the trimming, forming a high-k metal gate in the gate trench.

公开(公告)号：US20240387511A1

公开(公告)日：2024-11-21

申请号：US18789462

申请日：2024-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Feng CHANG ,  Jam-Wem LEE

IPC: H01L27/02

Abstract: A semiconductor device is provided, including a first well of a first conductivity type disposed on a substrate, a second well of a second conductivity type, different from the conductivity type, surrounding the first well in a layout view, a third well of the first conductivity type, in which a portion of the second well is interposed between the first well and the third well, a first doped region of the second conductivity type that is in the first well and coupled to an input/output (I/O) pad; and at least one second doped region of the first conductivity type that is in the third well and coupled to a first supply voltage terminal. The first doped region, the at least one second doped region, the first well and the third well discharge a first electrostatic discharge (ESD) current between the I/O pad and the first voltage terminal.

公开(公告)号：US20240387504A1

公开(公告)日：2024-11-21

申请号：US18785842

申请日：2024-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Liang CHEN ,  Shun Li CHEN ,  Li-Chun TIEN ,  Ting Yu CHEN ,  Hui-Zhong ZHUANG

IPC: H01L27/02 ,  G06F30/392 ,  H01L27/092

Abstract: An integrated circuit (IC) device includes first to fourth circuits configured to perform corresponding functions. The first to fourth circuits correspondingly include first to fourth active regions extending along a first direction, and further include a plurality of gate regions extending along a second direction transverse to the first direction. Adjacent gate regions among the plurality of gate regions are spaced from each other along the first direction by one gate region pitch. The first active region and the second active region correspondingly have a first source/drain region and a second source/drain region spaced from each other, along the first direction, by one gate region pitch. The first source/drain region is a drain region. The plurality of gate regions includes a dummy gate region between the first source/drain region and the second source/drain region. The third active region and the fourth active region share a common source region.

公开(公告)号：US20240387491A1

公开(公告)日：2024-11-21

申请号：US18455857

申请日：2023-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen

IPC: H01L25/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A method includes bonding a module over a package component. The module includes a substrate and through-vias penetrating through the substrate. The method further includes molding the module in a molding compound, bonding an electronic die on the module, and bonding a photonic die over the electronic die.