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    TESTING OF COMPARATORS WITHIN A MEMORY SAFETY LOGIC CIRCUIT USING A FAULT ENABLE GENERATION CIRCUIT WITHIN THE MEMORY
    253.
    发明申请
    TESTING OF COMPARATORS WITHIN A MEMORY SAFETY LOGIC CIRCUIT USING A FAULT ENABLE GENERATION CIRCUIT WITHIN THE MEMORY 审中-公开

    公开(公告)号：US20200219579A1

    公开(公告)日：2020-07-09

    申请号：US16702744

    申请日：2019-12-04

    Applicant: STMicroelectronics International N.V.

    Inventor： Rohit BHASIN ,  Shishir KUMAR ,  Tanmoy ROY ,  Deepak Kumar BIHANI

    IPC: G11C29/38 ,  G11C29/14

    Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

    Method and circuit for adaptive read-write operation in self-timed memory
    255.
    发明授权
    Method and circuit for adaptive read-write operation in self-timed memory 有权

    公开(公告)号：US10706915B2

    公开(公告)日：2020-07-07

    申请号：US16351773

    申请日：2019-03-13

    Applicant: STMicroelectronics International N.V.

    Inventor： Abhishek Pathak ,  Tanmoy Roy ,  Shishir Kumar

    IPC: G11C7/00 ,  G11C11/412 ,  G11C7/14 ,  G11C11/419 ,  G11C8/08 ,  G11C11/413 ,  G11C11/418

    Abstract: A memory device includes first and second dummy word line portions. A dummy word line driver drives the first dummy word line portion. A voltage dropping circuit causes a voltage on the second dummy word line to be less than a voltage on the first dummy word line. At least one dummy memory cell is coupled to the second dummy word line portion, remains in standby until assertion of the second dummy word line, and performs a dummy cycle in response to assertion of the second dummy word line. A reset signal generation circuit generates a reset signal in response to completion of a dummy cycle by the at least one dummy memory cell. An internal clock signal is generated from an external clock signal and the reset signal and is used in performing a read and/or write cycle to a memory array.

    Dynamic element matching of resistors in a sensor
    257.
    发明授权
    Dynamic element matching of resistors in a sensor 有权

    公开(公告)号：US10686442B2

    公开(公告)日：2020-06-16

    申请号：US15783897

    申请日：2017-10-13

    Applicant: STMicroelectronics International N.V.

    Inventor： Tanmoy Sen ,  Aswani Aditya Kumar Tadinada

    IPC: H03K19/00 ,  H03K19/003

    Abstract: A method and apparatus for dynamically matching a plurality of resistors to a sensor are disclosed. In the method and apparatus, a switching block of a plurality of switching blocks receives a plurality of selection signals. The switching block is coupled to a resistor array having a plurality of resistors that are coupled in series and arranged in a closed loop. Each two resistors are coupled to each other by a respective resistor node of a plurality of resistor nodes. The switching block of the plurality of switching blocks has a plurality of input nodes and an output node, where the output node is coupled to the respective resistor node of the plurality of resistor nodes. In the method and apparatus, the switching block couples an input node of the plurality of input nodes to the output node based on the selection signals.

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