公开(公告)号：US10142101B2

公开(公告)日：2018-11-27

申请号：US14868579

申请日：2015-09-29

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  Jason W Brandt

IPC: H04L9/08 ,  H04L9/32 ,  G06F21/00 ,  H04L9/06 ,  G06F21/60

Abstract: Embodiments of an invention for hardware enforced one-way cryptography are disclosed. In one embodiment, a processor includes a processor key location, instruction hardware, and execution hardware. The processor key location is to hold a processor key. The instruction hardware is to receive a first instruction in an instruction set of the processor. The first instruction is to encrypt input data with the processor key and return a handle. The instruction set lacks a second instruction corresponding to the first instruction to decrypt the handle with the processor key to return the input data. The execution hardware is to perform, in response to receipt of the first instruction by the instruction hardware, encryption of the input data with the processor key and to return the handle.

公开(公告)号：US10128868B1

公开(公告)日：2018-11-13

申请号：US15858964

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Yen-Kuang Chen

IPC: H03M7/34 ,  H03M7/30

Abstract: Various systems and methods for lossless data compression are described herein. A process for lossless data compression includes hashing an input byte stream to produce a hash key; identifying a set of dictionary entries in a hash table using the hash key, the hash key associated with a word from a compact dictionary; identifying a set of candidate words from the compact dictionary based on the identified set of dictionary entries, the compact dictionary being a subset of a standard dictionary; determining a best match of the set of candidate words with the input byte stream; and encoding the best match of the set of candidate words as a compressed output of the input byte stream, the encoding including an operation to determine an index into the standard dictionary of the best match and using the index in the encoding operation.

公开(公告)号：US10127042B2

公开(公告)日：2018-11-13

申请号：US15396578

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kirk S. Yap ,  Gilbert M. Wolrich ,  James D. Guilford ,  Vinodh Gopal ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

IPC: G06F9/30 ,  G06F21/60 ,  G06F15/80 ,  G06F9/38 ,  G06F12/0897 ,  G06F12/0875 ,  G06F12/1027 ,  G06F13/40 ,  G06F13/42 ,  H04L9/06

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：US10116327B2

公开(公告)日：2018-10-30

申请号：US15638842

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Daniel F. Cutter ,  Vinodh Gopal ,  James D. Guilford

IPC: H03M7/30 ,  G06F17/30

Abstract: Technologies for compressing data with multiple hash tables include a compute device. The compute device is to produce, for each of multiple string prefixes of different string prefix sizes, an associated hash. Each string prefix defines a set of consecutive symbols in a string that starts at a present position in an input stream of symbols. The compute device is also to write, to a different hash table for each string prefix size, a pointer to the present position in association with the associated hash. Each hash is usable as an index into the associated hash table to provide the present position of the string.

公开(公告)号：US20180310012A1

公开(公告)日：2018-10-25

申请号：US15496562

申请日：2017-04-25

Applicant: Intel Corporation

Inventor： Gregory B. Tucker ,  James D. Guilford ,  Daniel F. Cutter ,  Vinodh Gopal ,  Wajdi K. Feghali

IPC: H04N19/426 ,  H04N19/66

CPC classification number: H03M7/40 ,  H03M7/3086 ,  H03M7/4043

Abstract: Methods and apparatus are described by which data is compressed using semi-dynamic Huffman code generation. Embodiments generate symbol statistics over a portion of data. The symbol statistics are expanded to include all possible literals that could appear within the data. Any literal or reference added to the statistics may be given a frequency of one. The statistics are used to generate a semi-dynamic Huffman code. The entire data is then compressed using the semi-dynamic Huffman code.

公开(公告)号：US10103877B2

公开(公告)日：2018-10-16

申请号：US14864227

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Sudhir K. Satpathy ,  Sanu K. Mathew ,  Kirk S. Yap ,  Vinodh Gopal

IPC: G06F9/30 ,  G06F21/60 ,  H04L9/28 ,  H04L9/06 ,  H04L9/14

Abstract: A processing system includes a memory and a processing logic operatively coupled to the memory. The processing logic identifies one or more constant bits of an output bit sequence. The processing logic generates a plurality of variable bits of the output bit sequence. The processing logic produces the output bit sequence including the identified constant bits and the generated plurality of variable bits.

公开(公告)号：US10097201B1

公开(公告)日：2018-10-09

申请号：US15828137

申请日：2017-11-30

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  Daniel F. Cutter

IPC: H03M7/40 ,  H03M7/30

Abstract: Methods and apparatus are described by for compressing data using LZ77 compression. Embodiments determine an initial run from input data. The initial run includes repeating data at a first location and has a first length. A hash chain is updated with a proper set of hashes from prefixes from the initial run. A first search engine determines a second run that includes the repeating data at a second location. The second run has a second length less than the first length. A first matching location is determined within the input data having the repeating data using the hash chain and the second run. The first matching location is the first location. The first matching location, the second location, and the second length are written to an output buffer. The output buffer includes a compressed version of the input data.

公开(公告)号：US10038550B2

公开(公告)日：2018-07-31

申请号：US13962933

申请日：2013-08-08

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  Wajdi K. Feghali

IPC: H04L9/06

CPC classification number: H04L9/0643 ,  G06F9/30007 ,  G06F9/30036 ,  H04L9/0625

Abstract: Instructions and logic provide secure cipher hashing algorithm round functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a secure cipher hashing algorithm, the first instruction specifying a source data, and one or more key operands. Processor execution units, are responsive to the decoded instruction, to perform one or more secure cipher hashing algorithm round iterations upon the source data, using the one or more key operands, and store a result of the instruction in a destination register. One embodiment of the instruction specifies a secure cipher hashing algorithm round iteration using a Feistel cipher algorithm such as DES or TDES. In one embodiment a result of the instruction may be used in generating a resource assignment from a request for load balancing requests across the set of processing resources.

公开(公告)号：US20180164864A1

公开(公告)日：2018-06-14

申请号：US15379283

申请日：2016-12-14

Applicant: Intel Corporation

Inventor： Simon N. Peffers ,  Sean M. Gulley ,  Thomas L. Dmukauskas ,  Aaron Gorius ,  Vinodh Gopal

IPC: G06F1/28 ,  G01R31/28 ,  G06F1/32

CPC classification number: G06F1/3296 ,  G01R31/2856 ,  G01R31/2874 ,  G01R31/2879 ,  G06F1/3206 ,  G06F1/324 ,  G06F11/24 ,  Y02D10/126 ,  Y02D10/172

Abstract: Methods and apparatuses related to guardband recovery using in situ characterization are disclosed. In one example, a system includes a target circuit, a voltage regulator to provide a variable voltage to, a phase-locked loop (PLL) to provide a variable clock to, and a temperature sensor to sense a temperature of the target circuit, and a control circuit, wherein the control circuit is to set up a characterization environment by setting a temperature, voltage, clock frequency, and workload of the target circuit, execute a plurality of tests on the target circuit, when the target circuit passes the plurality of tests, adjust the variable voltage to increase a likelihood of the target circuit failing the plurality of tests and repeat the plurality of tests, and when the target circuit fails the plurality of tests, adjust the variable voltage to decrease a likelihood of the target circuit failing the plurality of tests.

公开(公告)号：US09996708B2

公开(公告)日：2018-06-12

申请号：US14751995

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Sudhir K. Satpathy ,  Sanu K. Mathew ,  Kirk S. Yap ,  Vinodh Gopal

IPC: G06F11/30 ,  G06F12/14 ,  G06F21/74 ,  G09C1/00 ,  H04L9/06

CPC classification number: G06F21/74 ,  G06F21/73 ,  G06F2221/2107 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/122

Abstract: A processing system includes a processing core and a hardware accelerator communicatively coupled to the processing core. The hardware accelerator includes a data register having a plurality of data bits and a key register having a plurality of key bits. The hardware accelerator also includes a data mode selector module to select one of an encrypt mode or a decrypt mode for processing the plurality of data bits. The hardware accelerator further includes a key mode selector module to select one of the encrypt mode or the decrypt mode for processing the plurality of key bits.