公开(公告)号：US5913704A

公开(公告)日：1999-06-22

申请号：US855425

申请日：1997-05-12

Applicant: Christopher J. Spindt ,  John M. Macaulay ,  Robert M. Duboc, Jr. ,  Peter C. Searson

Inventor： Christopher J. Spindt ,  John M. Macaulay ,  Robert M. Duboc, Jr. ,  Peter C. Searson

IPC: H01J1/30 ,  H01J1/304 ,  H01J3/02 ,  H01J9/02 ,  H01J29/04 ,  H01J31/12

CPC classification number: B82Y10/00 ,  H01J1/3042 ,  H01J3/022 ,  H01J9/025 ,  H01J2201/30403 ,  H01J2201/30457 ,  H01J2201/319

Abstract: Gated electron emitters are fabricated by processes in which charged particles are passed through a track layer (24, 48, or 144) to form charged-particle tracks (26.sub.1, 50.sub.1, or 146.sub.1). The track layer is etched along the tracks to create open spaces (28.sub.1, 52.sub.1, or 148.sub.1). Electron-emissive elements (30 or 142D) can then be formed at locations respectively centered on the open spaces after which a patterned gate layer (34B, 40B, or 158C) is provided. Alternatively, the open spaces in the track layer can be employed to etch corresponding apertures (54.sub.1) through an underlying non-insulating layer (46) which typically serves as the gate layer. An etch is performed through the apertures to form dielectric open spaces (56.sub.1, 96.sub.1, or 114.sub.1) in an insulating layer (24) that lies below the non-insulating layer. Electron-emissive elements (30B, 30/88D.sub.1, 98/102.sub.1, or 118.sub.1) can subsequently be provided, typically in the dielectric open spaces.

Abstract translation: 门电子发射器通过其中带电粒子通过轨道层（24,48或144）以形成带电粒子轨道（261,501或1461）的工艺制造。 轨道层沿着轨道被蚀刻以创建开放空间（281,521或1481）。 然后可以在分开以开放空间为中心的位置处形成电子发射元件（30或142D），之后设置图案化栅极层（34B，40B或158C）。 或者，轨道层中的开放空间可用于通过通常用作栅极层的下面的非绝缘层（46）蚀刻相应的孔（541）。 通过孔进行蚀刻，以在位于非绝缘层下方的绝缘层（24）中形成介电开放空间（561,961或1141）。 随后可以提供电子发射元件（30B，30 / 88D1,98 / 1011或1181），通常在电介质开放空间中。

公开(公告)号：US5886460A

公开(公告)日：1999-03-23

申请号：US974757

申请日：1997-11-20

Applicant: Gary W. Jones ,  Steven M. Zimmerman ,  Jeffrey A. Silvernail ,  Susan K. Schwartz Jones

Inventor： Gary W. Jones ,  Steven M. Zimmerman ,  Jeffrey A. Silvernail ,  Susan K. Schwartz Jones

IPC: H01J1/304 ,  H01J3/02 ,  H01J9/02 ,  H01J19/24

CPC classification number: H01J9/025 ,  H01J3/022 ,  H01J2201/319 ,  H01J2329/00 ,  Y10S428/938

Abstract: A field emitter device formed by a veil process wherein a protective layer comprising a release layer is deposited on the gate electrode layer for the device, with the protective layer overlying the circumscribing peripheral edge of the opening of the gate electrode layer, to protect the edge of the gate electrode layer during etching of the field emitter cavity in the dielectric material layer on a substrate, and during the formation of a field emitter element in the cavity by depositing a field emitter material through the opening. The protective layer is readily removed subsequent to completion of the cavity etching and emitter formation steps, to yield the field emitter device. Also disclosed are various planarizing structures and methods, and current limiter compositions permitting high efficiency emission of electrons from the field emitter elements at low turn-on voltages.

Abstract translation: 通过面纱工艺形成的场致发射体器件，其中包含释放层的保护层沉积在器件的栅极电极层上，其中保护层覆盖栅极电极层的开口的外接边缘，以保护边缘 在栅极电极层的蚀刻期间，在衬底中的电介质材料层中的场致发射器空腔的蚀刻期间，以及在通过开口沉积场致发射体材料在空腔中形成场发射极元件期间。 在腔蚀刻和发射极形成步骤完成之后，保护层容易去除，以产生场致发射器件。 还公开了各种平面化结构和方法，以及允许在低导通电压下从场致发射体元件高效发射电子的限流器组合物。

公开(公告)号：US5847504A

公开(公告)日：1998-12-08

申请号：US690895

申请日：1996-08-01

Applicant: Livio Baldi

Inventor： Livio Baldi

IPC: G09G3/22 ,  H01J1/304 ,  H01J31/12 ,  H01J1/62 ,  H01J1/02 ,  H01J1/16 ,  H01J63/04

CPC classification number: G09G3/22 ,  H01J1/3042 ,  H01J31/127 ,  H01J2201/30403 ,  H01J2201/319 ,  H01J2329/00

Abstract: A pixel emission current limiting resistance is realized by forming a stack of alternately doped amorphous or polycrystalline silicon layers over the cathodic conductors of a FED driving matrix. The stack of amorphous or polycrystalline silicon layers doped alternately n and p provides at least a reversely biased n/p junction having a leakage current that matches the required level of pixel emission current. The reversely biased junction constitutes a nonlinear series resistance that is quite effective in limiting the emission current through any one of the microtips that form an individually excitable pixel and which are formed on the uppermost layer of the stack.

Abstract translation: 通过在FED驱动矩阵的阴极导体上形成交替掺杂的非晶或多晶硅层的堆叠来实现像素发射电流限制电阻。 掺杂交替地n和p的非晶或多晶硅层的堆叠提供至少一个具有与所要求的像素发射电流水平匹配的漏电流的反向偏置n / p结。 反向偏置的结构成非线性串联电阻，其非常有效地限制通过形成可单独激发的像素并且形成在堆叠的最上层上的任何一个微尖端的发射电流。

公开(公告)号：US5834883A

公开(公告)日：1998-11-10

申请号：US950515

申请日：1997-10-23

Applicant: Marie-Dominique Bruni ,  Jean-Frederic Clerc

Inventor： Marie-Dominique Bruni ,  Jean-Frederic Clerc

IPC: H01J1/304 ,  H01J3/02 ,  H01J1/30

CPC classification number: B82Y10/00 ,  H01J1/3042 ,  H01J3/022 ,  H01J2201/319 ,  H01J2329/00

Abstract: A cathode includes microtips for flat display screens, of the type including cathode conductors, between a substrate and a gate, the gate including holes inside meshes defined by the cathode conductors. An insulating layer, including wells facing the holes, is interposed between the cathode conductors and the gate. Microtips are deposited in the wells, onto a resistive layer. The cathode conductors are deposited over the resistive layer and are coated with an auxiliary insulating layer.

Abstract translation: 阴极包括用于平面显示屏的微型插头，包括阴极导体，衬底和栅极之间的类型，栅极包括由阴极导体限定的网孔内的孔。 包括面向孔的阱的绝缘层插入在阴极导体和栅极之间。 微孔沉积在孔中，到电阻层上。 阴极导体沉积在电阻层上并涂覆有辅助绝缘层。

公开(公告)号：US5828288A

公开(公告)日：1998-10-27

申请号：US518745

申请日：1995-08-24

Applicant: Gary W. Jones ,  Steven M. Zimmerman ,  Susan K. Schwartz Jones ,  Michael J. Costa ,  Jeffrey A. Silvernail

Inventor： Gary W. Jones ,  Steven M. Zimmerman ,  Susan K. Schwartz Jones ,  Michael J. Costa ,  Jeffrey A. Silvernail

IPC: H01J1/304 ,  H01C7/00

CPC classification number: H01J1/3042 ,  H01J2201/30423 ,  H01J2201/319

Abstract: A microelectronic field emitter device comprising a substrate, a conductive pedestal on said substrate, and an edge emitter electrode on said pedestal, wherein the edge emitter electrode comprises an emitter cap layer having an edge. The invention also contemplates a current limiter for a microelectronic field emitter device, which comprises a semi-insulating material selected from the group consisting of SiO, SiO+Cr (0 to 50% wt.), SiO2+Cr (0 to 50% wt.), SiO+Nb, Al2O3 and SixOyNz sandwiched between an electron injector and a hole injector. Another aspect of the invention relates to a microelectronic field emitter device comprising a substrate, an emitter conductor on such substrate, and a current limiter stack formed on said substrate, such stack having a top and at least one edge, a resistive strap on top of the stack, extending over the edge in electrical contact with the emitter conductor; and an emitter electrode on the current limiter stack over the resistive strap.

Abstract translation: 一种微电子场发射器件，包括衬底，所述衬底上的导电基座和所述基座上的边缘发射极，其中所述边缘发射电极包括具有边缘的发射极帽层。 本发明还考虑了一种用于微电子场发射器件的电流限制器，其包括选自由SiO，SiO + Cr（0至50％重量），SiO 2 + Cr（0至50重量％）组成的组的半绝缘材料 ），夹在电子注入器和空穴注入器之间的SiO + Nb，Al2O3和SixOyNz。 本发明的另一方面涉及一种微电子场发射器件，其包括衬底，在该衬底上的发射极导体，以及形成在所述衬底上的限流器叠层，该堆叠具有顶部和至少一个边缘， 堆叠，在与发射极导体电接触的边缘上延伸; 并且电流限制器堆叠上的电阻带上的发射极电极。

公开(公告)号：US5827099A

公开(公告)日：1998-10-27

申请号：US568885

申请日：1995-12-07

Applicant: Christopher J. Spindt ,  John M. Macaulay ,  Robert M. Duboc, Jr. ,  Peter C. Searson

Inventor： Christopher J. Spindt ,  John M. Macaulay ,  Robert M. Duboc, Jr. ,  Peter C. Searson

IPC: H01J1/30 ,  H01J1/304 ,  H01J3/02 ,  H01J9/02 ,  H01J29/04 ,  H01J31/12

CPC classification number: B82Y10/00 ,  H01J1/3042 ,  H01J3/022 ,  H01J9/025 ,  H01J2201/30403 ,  H01J2201/30457 ,  H01J2201/319

Abstract: Gated electron emitters are fabricated by processes in which charged particles are passed through a track layer (24, 48, or 144) to form charged-particle tracks (26.sub.1, 50.sub.1, or 146.sub.1). The track layer is etched along the tracks to create open spaces (28.sub.1, 52.sub.1, or 148.sub.1). Electron-emissive elements (30 or 142D) can then be formed at locations respectively centered on the open spaces after which a patterned gate layer (34B, 40B, or 158C) is provided. Alternatively, the open spaces in the track layer can be employed to etch corresponding apertures (54.sub.1) through an underlying non-insulating layer (46) which typically serves as the gate layer. An etch is performed through the apertures to form dielectric open spaces (56.sub.1, 96.sub.1, or 114.sub.1) in an insulating layer (24) that lies below the non-insulating layer. Electron-emissive elements (30B, 30/88D.sub.1, 98/102.sub.1, or 118.sub.1) can subsequently be provided, typically in the dielectric open spaces.

Abstract translation: 门电子发射器通过其中带电粒子通过轨道层（24,48或144）以形成带电粒子轨道（261,501或1461）的工艺制造。 轨道层沿着轨道被蚀刻以创建开放空间（281,521或1481）。 然后可以在分开以开放空间为中心的位置处形成电子发射元件（30或142D），之后设置图案化栅极层（34B，40B或158C）。 或者，轨道层中的开放空间可用于通过通常用作栅极层的下面的非绝缘层（46）蚀刻相应的孔（541）。 通过孔进行蚀刻，以在位于非绝缘层下方的绝缘层（24）中形成介电开放空间（561,961或1141）。 随后可以提供电子发射元件（30B，30 / 88D1,98 / 1011或1181），通常在电介质开放空间中。

公开(公告)号：US5821680A

公开(公告)日：1998-10-13

申请号：US731651

申请日：1996-10-17

Applicant: John P. Sullivan ,  Thomas A. Friedmann

Inventor： John P. Sullivan ,  Thomas A. Friedmann

IPC: H01J1/304 ,  H01J9/02 ,  H01J19/24

CPC classification number: H01J9/025 ,  H01J1/304 ,  H01J2201/319

Abstract: A multi-layer resistive carbon film field emitter device for cold cathode field emission applications. The multi-layered film of the present invention consists of at least two layers of a conductive carbon material, preferably amorphous-tetrahedrally coordinated carbon, where the resistivities of adjacent layers differ. For electron emission from the surface, the preferred structure can be a top layer having a lower resistivity than the bottom layer. For edge emitting structures, the preferred structure of the film can be a plurality of carbon layers, where adjacent layers have different resistivities. Through selection of deposition conditions, including the energy of the depositing carbon species, the presence or absence of certain elements such as H, N, inert gases or boron, carbon layers having desired resistivities can be produced.

Abstract translation: 一种用于冷阴极场发射应用的多层电阻碳膜场发射极器件。 本发明的多层膜由至少两层导电碳材料组成，优选非晶四面体配位的碳，其中相邻层的电阻率不同。 对于来自表面的电子发射，优选的结构可以是具有比底层更低的电阻率的顶层。 对于边缘发射结构，膜的优选结构可以是多个碳层，其中相邻层具有不同的电阻率。 通过选择包括沉积碳物质的能量的沉积条件，可以产生具有所需电阻率的某些元素如H，N，惰性气体或硼的存在或不存在的碳层。

公开(公告)号：US5814925A

公开(公告)日：1998-09-29

申请号：US532985

申请日：1995-09-22

Applicant: Yoshinori Tomihari

Inventor： Yoshinori Tomihari

IPC: H01J1/304 ,  H01J3/02 ,  H01J1/30

CPC classification number: H01J3/022 ,  H01J2201/319

Abstract: An emissive electron source includes a first electrode (12) formed on an insulating substrate (1) in a form of mesh and a resistive coating (13) formed on the entire surface thereof. A plurality of cathodes (14) are disposed at the center of the mesh pattern to have the equal minimum distance between the respective cathodes (14) and the first electrode (12), and thereby improving the capability for limiting short-circuiting current in a resistive coating.

Abstract translation: 发射电子源包括形成在网状形式的绝缘基片（1）上的第一电极（12）和形成在其整个表面上的电阻涂层（13）。 多个阴极（14）设置在网状图案的中心处，以在各个阴极（14）和第一电极（12）之间具有相等的最小距离，从而提高限制短路电流的能力 电阻涂层。

公开(公告)号：US5814924A

公开(公告)日：1998-09-29

申请号：US457177

申请日：1995-06-01

Applicant: Hiroshi Komatsu

Inventor： Hiroshi Komatsu

IPC: H01J1/30 ,  H01J1/304 ,  H01J3/02 ,  H01J9/02 ,  H01J21/10 ,  H01L23/544 ,  H03F3/00

CPC classification number: B82Y10/00 ,  H01J1/3042 ,  H01J21/105 ,  H01J3/022 ,  H01J9/025 ,  H01L23/544 ,  H01J2201/30426 ,  H01J2201/319 ,  H01J2209/0226 ,  H01L2223/54473 ,  H01L2924/0002

Abstract: A display including plural field emission devices arranged in a pixel matrix. Each of these field emission devices includes an opening in an insulating layer of a supporting substrate, an upwardly extending cathode having a tip disposed centrally within the opening, and a gate electrode disposed circumferentially about the rim of the opening aligned substantially concentric to the cathode tip. Also, thin film transistor transmission gates are disposed proximate to each of the field emission devices and are selectively operable to control transmission of data signals to the gate electrode of the field emission devices to which they are adjacent.

Abstract translation: 包括以像素矩阵排列的多个场发射器件的显示器。 这些场致发射器件中的每一个包括在支撑衬底的绝缘层中的开口，具有设置在开口内部中心的尖端的向上延伸的阴极和围绕开口的边缘周向设置的栅极，该栅电极基本上与阴极尖端同心对准 。 此外，薄膜晶体管传输门靠近每个场发射器件设置，并且可选择性地操作以控制数据信号传输到与它们相邻的场发射器件的栅电极。

公开(公告)号：US5808403A

公开(公告)日：1998-09-15

申请号：US511261

申请日：1995-08-04

Applicant: Jean-Frederic Clerc

Inventor： Jean-Frederic Clerc

IPC: H01J9/02 ,  H01J1/304 ,  H01J29/04 ,  H01J31/12 ,  H01J1/30 ,  H01J19/24

CPC classification number: H01J1/3042 ,  H01J2201/319 ,  H01J2329/00

Abstract: A microtip cathode for flat panel display screens has a constant access resistance and includes a substrate (10), a resistive layer (19), at least one cathode conductor (13), an insulating layer (16), and a control gate (3). The microtip cathode further includes an auxiliary insulating layer (18) disposed between the cathode conductor (13) and the insulating layer (16) to suppress needle hole effects in the insulating layer (16).

Abstract translation: 用于平板显示屏的微尖端阴极具有恒定的访问阻力，并且包括基板（10），电阻层（19），至少一个阴极导体（13），绝缘层（16）和控制栅极 ）。 微尖端阴极还包括设置在阴极导体（13）和绝缘层（16）之间的辅助绝缘层（18），以抑制绝缘层（16）中的针孔效应。