公开(公告)号：US20070075791A1

公开(公告)日：2007-04-05

申请号：US11464946

申请日：2006-08-16

Applicant: Sebastien Dedieu ,  Jean-Francois Larchanche ,  Frederic Paillardet

Inventor： Sebastien Dedieu ,  Jean-Francois Larchanche ,  Frederic Paillardet

IPC: H03B5/12

CPC classification number: H03B5/04 ,  H03B5/1206 ,  H03B5/1253 ,  H03B5/1265

Abstract: An electronic circuit element has two capacitance values selected by means of a main control signal. The electronic circuit element comprises two variable-capacitance electronic components connected in parallel and each receiving opposite intermediate control signals, derived from the main control signal. The two variable-capacitance components are differentiated by a configuration parameter. The electronic circuit element exhibits a variation in capacitance corresponding to a difference between respective variations in capacitance of the two variable-capacitance electronic components during an inversion of the main control signal. The variation in capacitance of the electronic circuit element may be less than 5 attoFarads.

Abstract translation: 电子电路元件具有通过主控制信号选择的两个电容值。 电子电路元件包括并联连接的两个可变电容电子元件，并且各自接收来自主控制信号的相反的中间控制信号。 两个可变电容分量由配置参数区分。 电子电路元件在主控制信号的反转期间呈现出与两个可变电容电子部件的电容的各自变化的差异的电容变化。 电子电路元件的电容变化可能小于5attoFarads。

公开(公告)号：US20070074652A1

公开(公告)日：2007-04-05

申请号：US11523824

申请日：2006-09-14

Applicant: Didier Dutartre ,  Nicolas Loubet ,  Alexandre Talbot

Inventor： Didier Dutartre ,  Nicolas Loubet ,  Alexandre Talbot

IPC: C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC classification number: C30B25/18 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/02661

Abstract: A method for low-temperature epitaxy at the surface of at least one plate made of a pure silicon- or silicon alloy (SiGe, SiC, SiGeC . . . )-based material, in a chemical vapor deposition (CVD) system, in particular a rapid thermal (RTCVD) system, which method includes the following steps: loading the plate into the equipment, at a loading temperature, preparing the surface for the deposition of new chemical species, and after preparing the surface, performing the deposition under low-temperature epitaxy conditions (>750° C.), in which method the preparation of the surface includes a step of passivation of the surface by injection of an active gas, or gas mixture.

Abstract translation: 特别是在化学气相沉积（CVD）系统中由纯硅或硅合金（SiGe，SiC，SiGeC ...）基材料制成的至少一块板表面的低温外延方法 一种快速热（RTCVD）系统，该方法包括以下步骤：在装载温度下将板装载到设备中，制备用于沉积新化学物质的表面，并且在制备表面之后，在低温下进行沉积， 温度外延条件（> 750℃），其中制备表面的方法包括通过注入活性气体或气体混合物钝化表面的步骤。

公开(公告)号：US07193655B2

公开(公告)日：2007-03-20

申请号：US10782651

申请日：2004-02-19

Applicant: Marina Nicolas

Inventor： Marina Nicolas

IPC: H04N7/01

CPC classification number: H04N7/012 ,  H04N5/144 ,  H04N7/0137

Abstract: The invention provides for a process and a device for de-interlacing a video signal, wherein at output (S) is produced a signal (Sde) of video images de-interlaced by interpolating the pixels missing from the interlaced video signal presented at input (E), the interpolation on the output signal (Sde) being composed selectively (10) from a spatial interpolation (6), based on a transition detection and from a temporal interpolation (8) with a decision being made on the variable degree of presence of spatial interpolation and/or of temporal interpolation in the output signal (Sde), the decision being made as a function of a motion detection in the relevant area of the image, wherein the decision is made additionally as a function of a detection of the detail (2) in a relevant area of the image.

Abstract translation: 本发明提供了一种用于对视频信号进行去隔行扫描的过程和设备，其中在输出（S）处产生视频图像的信号（Sde），该视频图像通过内插来自在输入处呈现的隔行视频信号丢失的像素而被去隔行扫描 E），基于转移检测和来自对可变存在度的决定的时间插值（8），从空间插值（6）选择性地（10）地输出输出信号（Sde）上的内插 在所述输出信号（Sde）中进行空间插值和/或时间内插的判定，所述判定作为所述图像的相关区域中的运动检测的函数，其中，所述判定作为附加检测的函数 细节（2）在图像的相关区域。

公开(公告)号：US20070057700A1

公开(公告)日：2007-03-15

申请号：US11428471

申请日：2006-07-03

Applicant: Francois Jacquet ,  Thierry Devoivre

Inventor： Francois Jacquet ,  Thierry Devoivre

IPC: H03K5/22

CPC classification number: G11C15/04

Abstract: A content addressable memory (CAM) includes first and second memory circuits and a comparison circuit. The first memory circuit includes first and second sets of transistors for the storage of first and second compare data. The second memory circuit includes first and second sets of transistors for the storage of enabling or disabling data. The comparison circuit includes first and second sets of comparison transistors which respectively provide for the comparison of the first and second compare data with first and second input data under the control of an output signal from the second memory circuit. The transistors of the first and second sets of transistors of the memory circuits each includes a transistor of a first conductivity type and a transistor of a second conductivity type. The transistors of the second conductivity type are formed on the same first active zone of the semiconductor substrate. The first and second sets of comparison transistors of the comparison circuit are formed in separate active zones, respectively, which are mutually separated by the first active zone.

Abstract translation: 内容可寻址存储器（CAM）包括第一和第二存储器电路和比较电路。 第一存储器电路包括用于存储第一和第二比较数据的第一和第二组晶体管。 第二存储器电路包括用于存储启用或禁用数据的第一和第二组晶体管。 比较电路包括在第二存储器电路的输出信号的控制下分别提供第一和第二比较数据与第一和第二输入数据的比较的第一组和第二组比较晶体管。 存储电路的第一和第二组晶体管的晶体管各自包括第一导电类型的晶体管和第二导电类型的晶体管。 第二导电类型的晶体管形成在半导体衬底的相同的第一有源区上。 比较电路的第一组和第二组比较晶体管分别形成在由第一有源区相互隔开的分离的有源区中。

公开(公告)号：US07188038B2

公开(公告)日：2007-03-06

申请号：US10669083

申请日：2003-09-23

Applicant: Eric Picollet ,  Michel Minondo

Inventor： Eric Picollet ,  Michel Minondo

IPC: G01R19/00

CPC classification number: G01R27/2605

Abstract: A method of estimating an electrical capacitance of a circuit component is carried out by decomposing the capacitance into a sum of terms associated with respective contributions from a central part and peripheral parts of the component. A component to which the method can be applied comprises two rectangular conducting plates placed parallel to each other. One of the two plates is greater than the other. The component furthermore includes two different dielectrics. A first dielectric covers the large plate and separates the two plates, and a second dielectric surrounds the first plate and the first dielectric. A method of defining a dimension of a capacitor is also presented.

Abstract translation: 通过将电容分解成与来自组件的中心部分和外围部分的各自贡献相关联的项的总和来执行估计电路部件的电容的方法。 可以应用该方法的部件包括彼此平行放置的两个矩形导电板。 两块板块之一大于另一块。 该组件还包括两个不同的电介质。 第一电介质覆盖大板并分离两个板，并且第二电介质围绕第一板和第一电介质。 还提出了定义电容器尺寸的方法。

公开(公告)号：US07178044B2

公开(公告)日：2007-02-13

申请号：US10440044

申请日：2003-05-16

Applicant: Francesco Pappalardo ,  Luigi Mantellassi

Inventor： Francesco Pappalardo ,  Luigi Mantellassi

IPC: G06F1/26

CPC classification number: G06F9/30101 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  H01L23/34 ,  H01L2924/0002 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/171 ,  H01L2924/00

Abstract: A system-on-chip (SoC) architecture includes a plurality of blocks, each including a power control module to selectively control the power dissipated by the bloc. For each block, a power register is provided to receive power control instructions to selectively control the respective power control module. The system also includes a power control unit for writing respective power control instructions into the power control registers of the blocks, whereby the power dissipated is controlled individually and independently for each block under the centralized control of the power control unit. For each block, a power status register is also provided to receive status information concerning power control within the respective block. The power control unit reads the status instructions from such power status registers.

Abstract translation: 片上系统（SoC）架构包括多个块，每个块包括功率控制模块，用于选择性地控制由该块所耗散的功率。 对于每个块，提供功率寄存器以接收功率控制指令以选择性地控制相应的功率控制模块。 该系统还包括用于将各个功率控制指令写入块的功率控制寄存器的功率控制单元，由此在功率控制单元的集中控制下，对每个块单独且独立地控制功率消耗。 对于每个块，还提供功率状态寄存器以接收关于相应块内的功率控制的状态信息。 电源控制单元从这些电源状态寄存器读取状态指令。

公开(公告)号：US20060291273A1

公开(公告)日：2006-12-28

申请号：US11197737

申请日：2005-08-04

Applicant: Franck Genevaux

Inventor： Franck Genevaux

IPC: G11C7/02 ,  G11C11/00

CPC classification number: G11C11/412

Abstract: A memory cell comprises a first inverter (IA) and a second inverter (IB) coupled upside down to each other between a first node (A) and a second node (B), and a first access transistor (TA) having a drain coupled to the first node (A), a gate coupled to a word line (WL) and a source coupled to a bit line (BLREAD). The memory cell also comprises a reference transistor (TC) having a drain coupled to the first node (A) and a source coupled to a reference line (BLREF), a cut-off potential (GND) being applied to a gate of the reference transistor (TC). Also disclosed is a memory comprising memory cells as described here above, a write method and an associated read method.

Abstract translation: 存储单元包括在第一节点（A）和第二节点（B）之间彼此上下耦合的第一反相器（IA）和第二反相器（IB），以及具有漏极耦合的第一存取晶体管（TA） 到第一节点（A），耦合到字线（WL）的栅极和耦合到位线（BLREAD）的源极。 存储单元还包括具有耦合到第一节点（A）的漏极和耦合到参考线（BLREF）的源极的参考晶体管（TC），被施加到参考的栅极的截止电位（GND） 晶体管（TC）。 还公开了包括如上所述的存储器单元，写入方法和相关联的读取方法的存储器。

公开(公告)号：US20060259673A1

公开(公告)日：2006-11-16

申请号：US11398850

申请日：2006-04-05

Applicant: Frederic Bancel ,  Nicolas Berard

Inventor： Frederic Bancel ,  Nicolas Berard

IPC: G06F13/00

CPC classification number: G06F11/28

Abstract: A coprocessor includes a calculation unit for executing at least one command, and a securisation device. The securisation device includes an error detection circuit for monitoring the execution of the command so as to detect any execution error, putting the coprocessor into an error mode by default as soon as the execution of the command begins, and lifting the error mode at the end of the execution of the command if no error has been detected, an event detection circuit for monitoring the appearance of at least one event to be detected, and a masking circuit for masking the error mode while the event to be detected does not happen, and declaring the error mode to the outside of the coprocessor if the event to be detected happens while the coprocessor is in the error mode. Application in particular but not exclusively to coprocessors embedded in integrated circuits for smart cards.

Abstract translation: 协处理器包括用于执行至少一个命令的计算单元和安全化设备。 安全化装置包括用于监视命令的执行以检测任何执行错误的错误检测电路，一旦命令的执行开始，默认情况下将协处理器置于错误模式，并且在结束时提升错误模式 执行命令，如果没有检测到错误，则用于监视要检测的至少一个事件的外观的事件检测电路，以及用于在不发生检测事件的情况下屏蔽错误模式的屏蔽电路;以及 如果在协处理器处于错误模式时发生事件，则将错误模式声明为协处理器的外部。 尤其应用于嵌入在智能卡集成电路中的协处理器。

公开(公告)号：US20060252403A1

公开(公告)日：2006-11-09

申请号：US11399682

申请日：2006-04-05

Applicant: Patrice Garcia

Inventor： Patrice Garcia

IPC: H04B1/16 ,  H04M1/00

CPC classification number: H04B1/0057 ,  H04B1/406

Abstract: A receiver is provided for a wireless communication system that is operable in at least a first mode of communication and a second mode of communication. The receiver includes an antenna for receiving a communication signal, a BAW resonator for receiving an RF signal provided at an output of the antenna, a low noise amplifier, and a mixer circuit coupled to the low noise amplifier. The low noise amplifier has an adjustable input or output impedance for interacting with operating characteristics of the first BAW resonator. The mixer circuit mixes an RF signal with a signal from a local oscillator so as to generate an intermediary frequency. The input impedance of the low noise amplifier is adjusted so as to operate the receiver in the first or second mode of communication. Also provided is a wireless communication device (such as a cellular phone) that includes such a receiver.

Abstract translation: 为无线通信系统提供接收机，其可在至少第一通信模式和第二通信模式中操作。 接收机包括用于接收通信信号的天线，用于接收在天线的输出处提供的RF信号的BAW谐振器，低噪声放大器和耦合到低噪声放大器的混频器电路。 低噪声放大器具有可调节的输入或输出阻抗，用于与第一个BAW谐振器的工作特性相互作用。 混频器电路将RF信号与来自本地振荡器的信号进行混合，以产生中间频率。 调整低噪声放大器的输入阻抗，以便在第一或第二通信模式下操作接收机。 还提供了包括这种接收机的无线通信设备（诸如蜂窝电话）。

公开(公告)号：US07117474B2

公开(公告)日：2006-10-03

申请号：US10312125

申请日：2001-06-18

Applicant: Pierre-Yvan Liardet ,  Bruno Mussard

Inventor： Pierre-Yvan Liardet ,  Bruno Mussard

IPC: G06F17/50

CPC classification number: G11C16/22

Abstract: A circuit to detect the use of an element of an integrated circuit may include a non-volatile electrically programmable storage circuit and a programming circuit. The programming circuit may be used to partially program the storage circuit and gradually modify its programming level as the element is used so that the level represents the number of uses of the element.

Abstract translation: 用于检测集成电路元件的使用的电路可以包括非易失性电可编程存储电路和编程电路。 编程电路可以用于对存储电路进行部分编程，并且在使用元件时逐渐修改其编程级别，使得该级别表示元件的使用次数。