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公开(公告)号：US07408422B2
公开(公告)日：2008-08-05
申请号：US11464946
申请日：2006-08-16
IPC分类号： H03B5/18
CPC分类号： H03B5/04 , H03B5/1206 , H03B5/1253 , H03B5/1265
摘要： An electronic circuit element has two capacitance values selected by means of a main control signal. The electronic circuit element comprises two variable-capacitance electronic components connected in parallel and each receiving opposite intermediate control signals, derived from the main control signal. The two variable-capacitance components are differentiated by a configuration parameter. The electronic circuit element exhibits a variation in capacitance corresponding to a difference between respective variations in capacitance of the two variable-capacitance electronic components during an inversion of the main control signal. The variation in capacitance of the electronic circuit element may be less than 5 attoFarads.
摘要翻译： 电子电路元件具有通过主控制信号选择的两个电容值。 电子电路元件包括并联连接的两个可变电容电子元件，并且各自接收来自主控制信号的相反的中间控制信号。 两个可变电容分量由配置参数区分。 电子电路元件在主控制信号的反转期间呈现出与两个可变电容电子部件的电容的各自变化的差异的电容变化。 电子电路元件的电容变化可能小于5attoFarads。
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公开(公告)号：US20070075791A1
公开(公告)日：2007-04-05
申请号：US11464946
申请日：2006-08-16
IPC分类号： H03B5/12
CPC分类号： H03B5/04 , H03B5/1206 , H03B5/1253 , H03B5/1265
摘要： An electronic circuit element has two capacitance values selected by means of a main control signal. The electronic circuit element comprises two variable-capacitance electronic components connected in parallel and each receiving opposite intermediate control signals, derived from the main control signal. The two variable-capacitance components are differentiated by a configuration parameter. The electronic circuit element exhibits a variation in capacitance corresponding to a difference between respective variations in capacitance of the two variable-capacitance electronic components during an inversion of the main control signal. The variation in capacitance of the electronic circuit element may be less than 5 attoFarads.
摘要翻译： 电子电路元件具有通过主控制信号选择的两个电容值。 电子电路元件包括并联连接的两个可变电容电子元件，并且各自接收来自主控制信号的相反的中间控制信号。 两个可变电容分量由配置参数区分。 电子电路元件在主控制信号的反转期间呈现出与两个可变电容电子部件的电容的各自变化的差异的电容变化。 电子电路元件的电容变化可能小于5attoFarads。
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3.发明申请Method of correcting the phase difference between two input signals of a phase-locked loop and associated device 有权校正锁相环和相关设备的两个输入信号之间的相位差的方法公开(公告)号：US20060132245A1
公开(公告)日：2006-06-22
申请号：US11304382
申请日：2005-12-15
IPC分类号： H03L7/00
CPC分类号： H03L7/087 , H03L7/085 , H03L7/0895
摘要： A method for correcting the phase difference between two input signals of a phase-locked loop may include a charge pump connected to a filter. Prior to the occurrence of the first of the two input signals, a calibration phase may be carried out in which the input of the filter is disconnected from the output of the charge pump, the output voltage from the charge pump is equalized, to within a given error, with the input voltage of the filter, the amplitudes of the opposing currents flowing in the charge pump being equalized. Then, during the two respective occurrences of the two input signals, the input of the filter is reconnected to the output of the charge pump, and two phase-shifted signals that are delayed with respect to the input signals are respectively generated, in response to which the two opposing currents are, respectively and successively, interrupted, before the calibration phase is recommenced.
摘要翻译： 用于校正锁相环路的两个输入信号之间的相位差的方法可以包括连接到滤波器的电荷泵。 在发生两个输入信号中的第一个信号之前，可以执行校准阶段，其中滤波器的输入与电荷泵的输出断开，来自电荷泵的输出电压相等， 给定误差，在滤波器的输入电压下，在电荷泵中流动的相对电流的幅度相等。 然后，在两个输入信号的两个相应出现期间，滤波器的输入被重新连接到电荷泵的输出，并且分别产生相对于输入信号延迟的两个相移信号，响应于 在校准阶段重新开始之前，两个相对的电流分别和相继地中断。
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公开(公告)号：US5956262A
公开(公告)日：1999-09-21
申请号：US614862
申请日：1996-03-12
CPC分类号： H03H17/0226 , H03H17/0292 , H03H17/0607 , H03H17/0657 , H03H2218/10
摘要： A digital sample filtering device comprising storage device including ROM and RAM memory for storing in an interlaced manner, coefficients of at least two filters along with for each coefficient, data indicating to which of the filters the each coefficient belongs; a multiplier for multiplying at least one of the coefficients by a sample and an accumulator for adding the partial sums of the multiplication results for each of the filters.
摘要翻译： 一种数字样本滤波装置，包括存储装置，包括ROM和RAM存储器，用于以隔行方式存储至少两个滤波器的系数以及每个系数，指示每个系数属于哪个滤波器的数据; 乘法器，用于将系数中的至少一个乘以采样和累加器，用于将每个滤波器的相乘结果的部分和相加。
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5.发明授权Electronic component allowing the decoding of digital terrestrial or cable television signals 有权允许数字地面或有线电视信号解码的电子元件公开(公告)号：US07962949B2
公开(公告)日：2011-06-14
申请号：US10814621
申请日：2004-03-31
CPC分类号： H04N5/4446 , H03D3/007 , H03D7/161 , H04L2027/0016 , H04L2027/0024 , H04N5/4401 , H04N5/455 , H04N21/426 , H04N21/6112
摘要： A dual-conversion tuner firstly upconverts so as to place itself outside the receive band and then downconverts with zero intermediate frequency. A filter of the surface acoustic wave type is disposed between the two frequency transposition stages of the tuner. After baseband filtering, the signals are digitized then processed in a digital block comprising a channel decoding module. With the exception of the surface acoustic wave filter, the components are entirely embodied in integrated fashion.
摘要翻译： 首先将双转换调谐器上变频，将其自身置于接收频带外，然后以零中频下变频。 表面声波型滤波器设置在调谐器的两个频率转置级之间。 在基带滤波之后，信号被数字化，然后在包括信道解码模块的数字块中进行处理。 除了表面声波滤波器之外，组件完全以整体方式体现。
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6.发明申请METHOD FOR NOTCH FILTERING A DIGITAL SIGNAL, AND CORRESPONDING ELECTRONIC DEVICE 有权用于对数字信号进行过滤的方法和相应的电子设备公开(公告)号：US20090082006A1
公开(公告)日：2009-03-26
申请号：US12208921
申请日：2008-09-11
IPC分类号： H04W99/00
CPC分类号： H03H17/025 , H03M3/504
摘要： An electronic device, includes sigma-delta modulation circuit to operate with a clock signal and having output circuitry to deliver a digital data signal. First circuitry delivers a radiofrequency transposition signal. A notch filter includes radiofrequency digital-to-analog conversion blocks, having first input circuitry coupled to the output circuitry. Second input circuitry receives the radiofrequency transposition signal. Second output circuitry delivers a radiofrequency analog signal. Digital delay circuitry is controlled by the clock signal and includes a delay block between the two first input circuits. The frequency of a notch of the notch filter is related to the value of the delay from the delay block. Summation circuitry sums the radiofrequency signals.
摘要翻译： 电子设备包括用时钟信号操作并具有输出电路以输送数字数据信号的Σ-Δ调制电路。 第一个电路传送一个射频转置信号。 陷波滤波器包括射频数模转换块，其具有耦合到输出电路的第一输入电路。 第二输入电路接收射频转置信号。 第二输出电路提供射频模拟信号。 数字延迟电路由时钟信号控制，并且包括两个第一输入电路之间的延迟块。 陷波滤波器的陷波的频率与延迟块的延迟值有关。 求和电路对射频信号进行求和。
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公开(公告)号：US6125094A
公开(公告)日：2000-09-26
申请号：US66726
申请日：1998-04-23
摘要： A current amplifier includes a cascode transistor for fixing the voltage of an input of the amplifier; a first constant current source connected between the input and a first supply voltage; a second constant current source, for providing a current lower than the first current source, connected between a second supply voltage and the cascode transistor; a second transistor, of different type than the cascode transistor, connected between the input and the second supply voltage, and controlled by the node between the cascode transistor and the second current source; and an output transistor of same type as the second transistor, connected to the second supply voltage and controlled by the node.
摘要翻译： 电流放大器包括用于固定放大器的输入端的电压的共源共栅晶体管; 连接在所述输入端和第一电源电压之间的第一恒流源; 第二恒流源，用于提供连接在第二电源电压和共源共栅晶体管之间的低于第一电流源的电流; 第二晶体管，其不同于共源共栅晶体管的类型，连接在输入和第二电源电压之间，并由共源共栅晶体管和第二电流源之间的节点控制; 以及与第二晶体管相同类型的输出晶体管，连接到第二电源电压并由节点控制。
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8.发明申请公开(公告)号：US20090073013A1
公开(公告)日：2009-03-19
申请号：US12208966
申请日：2008-09-11
IPC分类号： H03M1/66
摘要： A method for processing a digital signal includes an elementary processing including a radiofrequency transposition with a radiofrequency transposition signal and a digital to analog conversion of the transposed digital signal for delivering a radiofrequency analog signal. The digital to analog conversion is controlled by a control signal and a power control signal, the control signal having a frequency twice the frequency of the radiofrequency transposition signal. Each transition of the radiofrequency transposition signal occurs between two consecutive pulses of said control signal.
摘要翻译： 用于处理数字信号的方法包括基本处理，其包括具有射频转置信号的射频转置和用于传递射频模拟信号的转置数字信号的数模转换。 数模转换由控制信号和功率控制信号控制，控制信号的频率是射频转置信号频率的两倍。 射频转置信号的每个转换发生在所述控制信号的两个连续脉冲之间。
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9.发明授权
公开(公告)号：US5696510A
公开(公告)日：1997-12-09
申请号：US443517
申请日：1995-05-18
CPC分类号： H03M1/1215 , H03M1/148 , H03M1/365
摘要： The disclosure is an analog-to-digital converter of half-flash type providing for the multiplexing of two analog input signals and therefore requiring only one converter module. It includes a coarse comparator block used to determine the most significant bits of the converted signals and also determining the voltage range for two fine comparator blocks that determine the least significant bits of the converted signals, wherein each of the input signals is connected to a fine comparator block and said coarse comparator block compares alternatively the first and second input signals with a reference voltage. The analog-to-digital converter can be advantageously used for processing television signals.
摘要翻译： 本公开是半闪存型的模数转换器，其提供两个模拟输入信号的复用，因此仅需要一个转换器模块。 它包括用于确定转换信号的最高有效位的粗略比较器块，并且还确定确定转换信号的最低有效位的两个精细比较器块的电压范围，其中每个输入信号被连接到一个精细 比较器块和所述粗略比较器块将第一和第二输入信号与参考电压进行比较。 模拟 - 数字转换器可以有利地用于处理电视信号。
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10.发明授权
公开(公告)号：US5684485A
公开(公告)日：1997-11-04
申请号：US503908
申请日：1995-07-18
摘要： The disclosure concerns a so-called "auto-zeroing" comparator of two analog input voltages to be compared, and an analog-to-digital converter using a set of auto-zeroing comparators enabling the number of comparators required for an analog-to-digital conversion to be reduced. The main originality of the invention is that this comparator includes a second stage constituted by an inverter function provided in such a way that only a first transistor is controlled on its gate by the previous stage, a second transistor having its gate and drain short-circuited by a switch during the auto-zeroing phase, and a third transistor used as a capacitor and connected to the gate of said second transistor and also to the supply voltage. The present invention is applicable in particular to all types of CMOS multi-comparison ADCs using at least one "auto-zeroing" comparator.
摘要翻译： 本公开涉及要比较的两个模拟输入电压的所谓“自动调零”比较器，以及使用一组自动归零比较器的模数转换器，使得能够使模拟 - 数字转换要减少。 本发明的主要原因在于该比较器包括由反相器功能构成的第二级，该反相器功能以仅在其栅极上由前一级控制第一晶体管的方式提供，其栅极和漏极短路的第二晶体管 通过在自动归零阶段期间的开关，以及用作电容器并连接到所述第二晶体管的栅极的第三晶体管以及电源电压。 本发明特别适用于使用至少一个“自动归零”比较器的所有类型的CMOS多比较ADC。
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