公开(公告)号：US11687460B2

公开(公告)日：2023-06-27

申请号：US15498076

申请日：2017-04-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael W. LeBeane ,  Walter B. Benton ,  Vinay Agarwala

IPC: G06F12/0817 ,  G06F12/1081 ,  G06F12/0831 ,  G06F12/0813 ,  G06F13/28

CPC classification number: G06F12/0828 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/1081 ,  G06F13/28 ,  G06F2212/1021 ,  G06F2212/154 ,  G06F2212/621 ,  G06F2212/622

Abstract: Methods, devices, and systems for GPU cache injection. A GPU compute node includes a network interface controller (NIC) which includes NIC receiver circuitry which can receive data for processing on the GPU, NIC transmitter circuitry which can send the data to a main memory of the GPU compute node and which can send coherence information to a coherence directory of the GPU compute node based on the data. The GPU compute node also includes a GPU which includes GPU receiver circuitry which can receive the coherence information; GPU processing circuitry which can determine, based on the coherence information, whether the data satisfies a heuristic; and GPU loading circuitry which can load the data into a cache of the GPU from the main memory if on the data satisfies the heuristic.

公开(公告)号：US11687456B1

公开(公告)日：2023-06-27

申请号：US17558393

申请日：2021-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Mei Ye

IPC: G06F12/0806

CPC classification number: G06F12/0806 ,  G06F2212/1016

Abstract: An electronic device that handles memory accesses includes a memory and a processor that supports a plurality of streams. The processor acquires a graph that includes paths of operations in a set of operations for processing instances of data through a model, each path of operations including a separate sequence of operations from the set of operations that is to be executed using a respective stream from among the plurality of streams. The processor then identifies concurrent paths in the graph, the concurrent paths being paths of operations between split points at which two or more paths of operations diverge and merge points at which the two or more paths of operations merge. The processor next executes operations in each of the concurrent paths using a respective stream, the executing including using memory coloring for handling memory accesses in the memory for the operations in each concurrent path.

公开(公告)号：US20230197623A1

公开(公告)日：2023-06-22

申请号：US17645104

申请日：2021-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Arsalan Alam ,  Raja Swaminathan ,  Rahul Agarwal

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/5384 ,  H01L24/14 ,  H01L23/49811 ,  H01L23/5385 ,  H01L23/5386

Abstract: An electronic device includes a first integrated circuit die, a support structure, and a second integrated circuit die and may include a spacer. The support structure includes a circuit element. The support structure has a thickness of at least 110 microns. The spacer or second integrated circuit die includes a conductor. The spacer or second integrated circuit die is disposed between the first integrated circuit die and the support structure. The conductor is electrically coupled to the integrated circuit die or the circuit element of the support structure. The electronic device provides more flexibility to a designer by allowing a circuit element or circuit that occupies a significant area to be in the support structure.

公开(公告)号：US20230196669A1

公开(公告)日：2023-06-22

申请号：US17553669

申请日：2021-12-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Matthäus G. Chajdas ,  Konstantin I. Shkurko

IPC: G06T17/00 ,  G06T15/06

CPC classification number: G06T17/005 ,  G06T15/06

Abstract: Devices and methods for using ray tracing to render similar but different objects in a scene are described which include rendering a second object using an overlay hierarchy tree. The overlay hierarchy tree comprises shared data from a base hierarchy tree comprising data representing a first object in the scene, a second hierarchy tree representing the second object in the scene, difference data representing a difference between the first object and the second object and indication information which indicates nodes of the overlay hierarchy tree comprising difference data.

公开(公告)号：US20230195889A1

公开(公告)日：2023-06-22

申请号：US17559520

申请日：2021-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Sudhanva Gurumurthi ,  Vilas Sridharan

IPC: G06F21/55 ,  G11C11/406 ,  G06F21/79

CPC classification number: G06F21/554 ,  G11C11/40618 ,  G11C11/40611 ,  G06F21/79

Abstract: A method and apparatus for mitigating row hammer attacks is provided. A row hammer alert is generated by a component of a memory architecture controlling operation of a memory device. The component may be a memory controller, coherency logic, or data fabric. The component obtains a physical address of an aggressor row that caused the alert and obtains an identifier of an execution context corresponding to the physical address. The component generates an error message for a processing device, the error message including the identifier of the execution context. The processing device retrieves the error message when performing a context switch. The processing device then generates an event received by the operating system. The operating system then takes action to reduce row hammer by the execution context, such as ending, restarting, or throttling the execution context.

公开(公告)号：US20230195666A1

公开(公告)日：2023-06-22

申请号：US17559984

申请日：2021-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander Sabino Duenas ,  Ashwini Chandrashekhara Holla ,  I-Cheng Chen ,  Xinzhe Li

IPC: G06F13/36 ,  G06F21/62

CPC classification number: G06F13/36 ,  G06F21/6218

Abstract: An electronic device includes a memory and a processor. The processor acquires a platform management profile, the platform management profile including information defining one or more platform management policies. The processor provides the platform management profile to platform management drivers executing on one or more electronic devices, the platform management profile being configured so that each of the platform management drivers can extract the one or more platform management policies from the platform management profile and use the one or more platform management policies for controlling operating states of elements (e.g., functional blocks, devices, etc.) of the respective electronic device.

公开(公告)号：US20230195664A1

公开(公告)日：2023-06-22

申请号：US17558798

申请日：2021-12-22

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Sean KEELY ,  Joseph L. GREATHOUSE ,  Hari THANGIRALA ,  Alan D. SMITH ,  Milind N. NEMLEKAR

IPC: G06F13/28 ,  G06F13/16

CPC classification number: G06F13/28 ,  G06F13/1668

Abstract: A method for software management of DMA transfer commands includes receiving a DMA transfer command instructing a data transfer by a first processor device. Based at least in part on a determination of runtime system resource availability, a device different from the first processor device is assigned to assist in transfer of at least a first portion of the data transfer. In some embodiments, the DMA transfer command instructs the first processor device to write a copy of data to a third processor device. Software analyzes network bus congestion at a shared communications bus and initiates DMA transfer via a multi-hop communications path to bypass the congested network bus.

公开(公告)号：US20230195644A1

公开(公告)日：2023-06-22

申请号：US17556617

申请日：2021-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Chintan S. Patel ,  Guhan Krishnan ,  Andrew William Lueck ,  Sreenath Thangarajan

IPC: G06F12/0897

CPC classification number: G06F12/0897 ,  G06F2212/60

Abstract: A data processor includes a data fabric, a memory controller, a last level cache, and a traffic monitor. The data fabric is for routing requests between a plurality of requestors and a plurality of responders. The memory controller is for accessing a volatile memory. The last level cache is coupled between the memory controller and the data fabric. The traffic monitor is coupled to the last level cache and operable to monitor traffic between the last level cache and the memory controller, and based on detecting an idle condition in the monitored traffic, to cause the memory controller to command the volatile memory to enter self-refresh mode while the last level cache maintains an operational power state and responds to cache hits over the data fabric.

公开(公告)号：US20230195640A1

公开(公告)日：2023-06-22

申请号：US17557731

申请日：2021-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Jeffrey Christopher Allan

IPC: G06F12/0893 ,  G06F12/0864

CPC classification number: G06F12/0893 ,  G06F12/0864 ,  G06F2212/604

Abstract: Cache associativity allocation is described. In accordance with the described techniques, a portion of associativity of a cache is allocated to a category of cache requests. The portion of associativity corresponds to a subset of cachelines of the cache. A request is received to access the cache, and a cacheline of the subset of cachelines is allocated to the request based on a category associated with the request. Data corresponding to the request is loaded into the cacheline of the subset of cachelines.

公开(公告)号：US20230195639A1

公开(公告)日：2023-06-22

申请号：US17557475

申请日：2021-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Saurabh Sharma ,  Jeremy Lukacs ,  Hashem Hashemi ,  Gianpaolo Tommasi ,  Christopher J. Brennan

IPC: G06F12/0893

CPC classification number: G06F12/0893 ,  G06F2212/6042

Abstract: A processing system selectively allocates storage at a local cache of a parallel processing unit for cache lines of a repeating pattern of data that exceeds the storage capacity of the cache. The processing system identifies repeating patterns of data having cache lines that have a reuse distance that exceeds the storage capacity of the cache. A cache controller allocates storage for only a subset of cache lines of the repeating pattern of data at the cache and excludes the remainder of cache lines of the repeating pattern of data from the cache. By restricting the cache to store only a subset of cache lines of the repeating pattern of data, the cache controller increases the hit rate at the cache for the subset of cache lines.