Protection Module for RF-Amplifier
    272.
    发明申请
    Protection Module for RF-Amplifier 有权
    射频放大器保护模块

    公开(公告)号:US20140368280A1

    公开(公告)日:2014-12-18

    申请号:US14375164

    申请日:2013-02-19

    Applicant: ST-Ericsson SA

    Inventor: Vincent Knopik

    Abstract: A protection module (4) for a RF-amplifier (2) is efficient against overvoltage due to load impedance mismatch when said RF-amplifier is connected to a load RF-element (3). The protection module comprises a branch with at least one diode-like operating component (D1, D2, . . . , Dn) and a resistor (R2) which starts conducting when a RF-signal on a transmission link (6) between the RF-amplifier and the load RF-element is higher than a threshold set by the diode-like operating component. Such protection may be implemented in MOS technology only.

    Abstract translation: 当所述RF放大器连接到负载RF元件(3)时,用于RF放大器(2)的保护模块(4)由于负载阻抗失配而有效地抵抗过电压。 该保护模块包括具有至少一个二极管状工作组件(D1,D2,...,Dn)和一个电阻器(R2)的分支,该电阻器(R2)在RF之间的传输链路(6)上的RF信号时开始传导, 放大器和负载RF元件高于由二极管状操作部件设置的阈值。 这种保护可以仅在MOS技术中实现。

    Detection of Change in Generated Magnetic Field Due to Tag-Loading
    273.
    发明申请
    Detection of Change in Generated Magnetic Field Due to Tag-Loading 有权
    由于标签加载而产生的磁场变化的检测

    公开(公告)号:US20140357190A1

    公开(公告)日:2014-12-04

    申请号:US14372052

    申请日:2013-02-01

    Applicant: ST-Ericsson SA

    CPC classification number: H04B5/0037 H04B5/0056 H04B5/0075 H04B5/0093

    Abstract: The invention concerns a Near Field Communication method comprising a step (1) of generating, by an antenna of a transmitter, a magnetic field (H), a step (2) of receiving, by an antenna of a tag, power from said generated magnetic field (H), then causing a drop in said generated magnetic field (H), wherein said method further comprises a step (3) of estimating said drop by sensing a voltage swing across said transmitter antenna.

    Abstract translation: 本发明涉及一种近场通信方法,包括步骤(1),其由发射机的天线产生磁场(H);步骤(2),其由标签的天线接收来自所述生成的 磁场(H),然后导致所述产生的磁场(H)的下降,其中所述方法还包括通过感测所述发射器天线之间的电压摆动来估计所述液滴的步骤(3)。

    CHARGE PUMP CIRCUIT
    274.
    发明申请
    CHARGE PUMP CIRCUIT 有权
    充电泵电路

    公开(公告)号:US20140307493A1

    公开(公告)日:2014-10-16

    申请号:US14354165

    申请日:2012-10-23

    Applicant: ST-Ericsson SA

    CPC classification number: H02M3/18 G05F3/00 H02M3/07 H02M2001/0054 Y02B70/1491

    Abstract: There is described a charge pump circuit (1) circuit comprising an input terminal, an output terminal (5) connected to an intermediate node (Ni), a ground terminal (4), a first fly capacitor module (21) with a first fly capacitor (Cfly1) having a first pin (211) and a second pin (212) and connected to the intermediate node (Ni); and a second fly capacitor module (22) with a first fly capacitor (Cfly2) having a first pin (221) and a second pin (222) and connected to the intermediate node (Ni); wherein each being adapted to successively charge and discharge a the first fly capacitor and the second fly capacitor, respectively, wherein the second pin (212) of the first fly capacitor module (21) is connected to the first pin (221) of the second fly capacitor module (22) by a direct connection.

    Abstract translation: 描述了一种电荷泵电路(1),包括输入端子,连接到中间节点(Ni)的输出端子(5),接地端子(4),具有第一飞行的第一飞行电容器模块(21) 电容器(Cfly1)具有第一引脚(211)和第二引脚(212)并连接到中间节点(Ni); 和具有第一引脚(221)和第二引脚(222)并连接到中间节点(Ni)的第一飞电容器(Cfly2)的第二飞电容器模块(22); 其中每个分别适于连续地对第一飞电容器和第二飞电容器进行充电和放电,其中第一飞电容器模块(21)的第二引脚(212)连接到第二飞电电容器的第二引脚(221) 飞电容器模块(22)通过直接连接。

    Downlink Signaling Counter Management for Multiple Subscriber Identity Devices
    275.
    发明申请
    Downlink Signaling Counter Management for Multiple Subscriber Identity Devices 有权
    用于多用户识别设备的下行链路信令计数器管理

    公开(公告)号:US20140295835A1

    公开(公告)日:2014-10-02

    申请号:US14353662

    申请日:2012-10-19

    Applicant: ST-Ericsson SA

    Inventor: Samuel Lamazure

    CPC classification number: H04W60/04 H04W60/005 H04W68/00

    Abstract: A downlink signaling counter management method is disclosed for a communication device adapted to be simultaneously associated with at least two subscriber identities and adapted to simultaneously provide radio receiving capabilities to less than all of the at least two subscriber identities. The method comprises, for each decoding of a paging block for a subscriber identity, determining whether the paging block decoding was correct and determining whether a previous paging block decoding condition is fulfilled. If the paging block decoding is correct, the downlink signaling counter is updated with a first value if the previous paging block decoding condition is fulfilled and with a second value if the previous paging block decoding condition is not fulfilled. If the paging block decoding is not correct and if the paging block decoding was based on a maximum number of paging bursts, the downlink signaling counter is updated with a third value if the previous paging block decoding condition is fulfilled and with a fourth value if the previous paging block decoding condition is not fulfilled. Corresponding computer program product, system and device are also disclosed.

    Abstract translation: 公开了用于适于与至少两个订户身份相关联并且适于同时向少于所有至少两个订户身份提供无线电接收能力的通信设备的下行链路信令计数器管理方法。 该方法包括:对于用户身份的寻呼块的每个解码,确定寻呼块解码是否正确,并确定是否满足先前的寻呼块解码条件。 如果寻呼块解码是正确的,则如果满足先前的寻呼块解码条件并且如果不满足先前的寻呼块解码条件,则以第一值更新下行链路信令计数器。 如果寻呼块解码不正确,并且如果寻呼块解码是基于寻呼突发的最大数量,则如果满足先前的寻呼块解码条件,则下行链路信令计数器被更新为第三值,并且如果 之前的寻呼块解码条件不能满足。 还公开了相应的计算机程序产品,系统和设备。

    Multi-Level Sigma-Delta ADC With Reduced Quantization Levels
    276.
    发明申请
    Multi-Level Sigma-Delta ADC With Reduced Quantization Levels 有权
    具有降低量化水平的多级Σ-ΔADC

    公开(公告)号:US20140247169A1

    公开(公告)日:2014-09-04

    申请号:US14351059

    申请日:2012-10-08

    Applicant: ST-Ericsson SA

    Inventor: Carlo Pinna

    CPC classification number: H03M3/422 H03M3/39 H03M3/424 H03M3/454

    Abstract: A multi-level sigma-delta Analog to Digital converter provides multi-level outputs using a quantizer with reduced quantization levels. The converter comprises a direct path comprising a computation block, an analog integrator and the quantizer with reduced quantization levels. Further, the converter comprises a feedback path arranged to provide to the computation block a feedback analog signal. The direct path comprises a first amplification block having a gain factor which is the inverse of the gain factor of a second amplification block of the feedback path. The converter allows reduction of the complexity of the quantizer.

    Abstract translation: 多电平Σ-Δ模数转换器使用具有降低量化级别的量化器来提供多电平输出。 转换器包括直接路径,其包括计算块,模拟积分器和具有降低量化级别的量化器。 此外,转换器包括反馈路径,其被布置为向计算块提供反馈模拟信号。 直接路径包括具有与反馈路径的第二放大块的增益因子相反的增益因子的第一放大块。 该转换器允许降低量化器的复杂性。

    Accumulating Data Values
    277.
    发明申请
    Accumulating Data Values 有权
    累积数据值

    公开(公告)号:US20140219320A1

    公开(公告)日:2014-08-07

    申请号:US14240576

    申请日:2012-09-28

    Applicant: ST-Ericsson SA

    Inventor: Arnaud Germain

    Abstract: An accumulation apparatus (230) for accumulating a number of data values comprises an adder (275) arranged, for each of the number of data values in turn, to add the data value to an adder sum present at an output (278) of the adder (275) for the preceding one of the data values. An asynchronous ripple counter (240) is coupled to the adder (275) for generating a ripple count by counting occurrences of overflow of the adder (275). The accumulation apparatus (230) provides an accumulated data value having the adder sum as its least significant part and the ripple count as its most significant part.

    Abstract translation: 用于累加多个数据值的累加装置(230)包括一个加法器(275),用于依次为多个数据值中的每一个数据值将数据值加到存在于该数据值的输出端(278)的加法器总和 加法器(275),用于前一个数据值。 异步纹波计数器(240)耦合到加法器(275),用于通过对加法器(275)的溢出进行计数来产生纹波计数。 累积装置(230)提供具有加法器和作为其最小有效部分的累积数据值,并且纹波计数作为其最重要部分。

    Polyphase Filter for MM-Wave Frequencies Featuring Symmetric Layout
    278.
    发明申请
    Polyphase Filter for MM-Wave Frequencies Featuring Symmetric Layout 有权
    具有对称布局的MM波频率的多相滤波器

    公开(公告)号:US20140176259A1

    公开(公告)日:2014-06-26

    申请号:US13722509

    申请日:2012-12-20

    Applicant: ST-ERICSSON SA

    CPC classification number: H03H7/06 H03H7/0138 H03H7/21 H03H2007/0192

    Abstract: A two-stage, passive, RC polyphase filter for mm-wave quadrature LO generation is presented. The filter features an innovative, symmetrical layout structure, which is more robust to parasitics than the conventional layout. Layout parasitics which become important at mm-wave frequencies are identified and a compensated. Impedance variations and transfer functions are evaluated considering these dominant parasitics. More than 15 dB improvement in image rejection ratio is achieved in comparison with conventional layouts. Using the inventive techniques more than 35 dB of image rejection ratio over a bandwidth of 6 GHz is demonstrated in an outphasing transmitter at 60 GHz in 40 nm CMOS.

    Abstract translation: 提出了一种用于毫米波正交LO生成的两级无源RC多相滤波器。 滤波器具有创新的对称布局结构,与传统布局相比,寄生效应更为鲁棒。 在mm波频率上变得重要的布局寄生效应被识别并得到补偿。 考虑到这些主要的寄生效应来评估阻抗变化和传递函数。 与传统布局相比,实现了超过15 dB的图像抑制比改善。 使用本发明的技术,在60GHz的40nm CMOS的外部发射机中证明了在6GHz的带宽上超过35dB的图像抑制比。

    Scheduling Best Effort Traffic With Guaranteed Latency Traffic In A Communications System Having A Bluetooth-Like Packet Communication Protocol
    279.
    发明申请
    Scheduling Best Effort Traffic With Guaranteed Latency Traffic In A Communications System Having A Bluetooth-Like Packet Communication Protocol 失效
    在具有类似蓝牙的分组通信协议的通信系统中调度具有保证的延迟业务的最佳努力业务

    公开(公告)号:US20140079030A1

    公开(公告)日:2014-03-20

    申请号:US13622762

    申请日:2012-09-19

    Applicant: ST-ERICSSON SA

    Inventor: Jorgen Van Parys

    CPC classification number: H04W72/12 H04W28/021 H04W28/10 H04W72/1242

    Abstract: Time frames (TFs) are allocated for performance of transactions of a low latency data stream (LLDS) and a best effort data stream (BEDS) in Bluetooth®-like equipment, wherein payload carrying packets of the different data streams are equal in size, each occupying multiple TFs. An overrule mechanism enables uncompleted transactions of one data stream to continue as needed into TFs allocated to another data stream. Every TF within an allocation window (AW) is individually allocated to the LLDS or the BEDS, and plural TFs immediately following the AW form a guard space between adjacent AWs, the guard space being allocated to neither the LLDDS or the BEDS. Configuration of the AW and of the guard space guarantees the LLDS a first opportunity to transmit a payload carrying packet and continued opportunities to retransmit the packet until successful, after which the BEDS is given an opportunity for transmission and possible retransmissions.

    Abstract translation: 时分帧(TF)被分配用于在蓝牙类设备中执行低延迟数据流(LLDS)和尽力数据流(BEDS)的事务,其中负载不同数据流的分组的负载的大小相等, 每个占用多个TF。 重叠机制使一个数据流的未完成事务可以根据需要继续分配给另一个数据流的TF。 分配窗口(AW)内的每个TF单独分配给LLDS或BEDS,并且AW之后的多个TF形成相邻AW之间的保护空间,保护空间既不分配给LLDDS也不分配给BEDS。 AW和保护空间的配置保证了LLDS第一次发送携带有效载荷的有效载荷的机会,并继续重新发送数据包的机会,直到成功,然后给予BEDS传输机会和可能的重传。

    Voltage Regulator
    280.
    发明申请
    Voltage Regulator 有权
    稳压器

    公开(公告)号:US20130027010A1

    公开(公告)日:2013-01-31

    申请号:US13632358

    申请日:2012-10-01

    Applicant: ST-Ericsson SA

    CPC classification number: G05F1/575

    Abstract: A voltage regulator includes a current bridge and first and second current paths coupling a current mirror to respective first and second voltage-to-current converters. The current mirror controls a second current dependent on a first current. The first voltage-to-current converter controls the first current dependent on either a reference voltage or a feedback voltage derived from the regulator's output voltage, and the second voltage-to-current converter controls the second current dependent on the other of the feedback and reference voltages. Voltage-to-current conversion by the first converter is independent of voltage-to-current conversion by the second converter. An output transistor stage coupled to the second current path controls the output voltage dependent on the voltage in the second current path indicative of a deviation of the second current from a target current value dependent on the reference voltage.

    Abstract translation: 电压调节器包括电流桥和将电流镜耦合到相应的第一和第二电压 - 电流转换器的第一和第二电流路径。 当前镜像控制依赖于第一电流的第二电流。 第一电压 - 电流转换器根据调节器的输出电压导出的参考电压或反馈电压来控制第一电流,而第二电压 - 电流转换器根据另一个反馈控制第二电流,并且 参考电压。 第一转换器的电压 - 电流转换与第二转换器的电压 - 电流转换无关。 耦合到第二电流路径的输出晶体管级根据第二电流路径中的电压控制输出电压,其指示第二电流与取决于参考电压的目标电流值的偏差。

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