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    Circuit for level shifting a clock signal using a voltage multiplier
    271.
    发明授权
    Circuit for level shifting a clock signal using a voltage multiplier 有权

    公开(公告)号：US10211727B1

    公开(公告)日：2019-02-19

    申请号：US16028814

    申请日：2018-07-06

    Applicant: STMicroelectronics International N.V.

    Inventor： Vikas Rana

    IPC: H02M3/18 ,  H02M3/07 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092

    Abstract: A voltage multiplier circuit operates in response to a received clock signal to perform a voltage multiplication operation on an input voltage to generate an output voltage. The voltage multiplier circuit includes a pair of intermediate nodes that are capacitively coupled to receive, respectively, opposite phases of a clock signal. A first CMOS driver circuit is coupled to one of the intermediate nodes and has an output configured to generate one phase of a level shifted output clock signal. A second CMOS driver circuit is coupled to another one of the intermediate nodes and has an output configured to generate another phase of the level shifted output clock signal.

    Non-volatile memory (NVM) with dummy rows supporting memory operations
    275.
    发明授权
    Non-volatile memory (NVM) with dummy rows supporting memory operations 有权

    公开(公告)号：US10127990B1

    公开(公告)日：2018-11-13

    申请号：US15652564

    申请日：2017-07-18

    Applicant: STMicroelectronics International N.V.

    Inventor： Vikas Rana

    IPC: G11C16/06 ,  G11C16/28 ,  G11C16/14 ,  G11C16/08

    Abstract: A memory array includes rows and columns with memory cell portion and a dummy cell portion. Bit lines are connected to the memory cells and to the dummy cell portion. The dummy cell portion includes a first row of dummy cells and a second row of dummy cells. The dummy cells in the first row have a first connection to a corresponding bit line of a first bit line group of the bit lines and a second connection to a first source line. The dummy cells in the second row have a first connection to a corresponding bit line of a second bit line group of the plurality of bit lines and a second connection to a second source line. The dummy cells are selectively actuated to couple voltages at the first and second source lines to the first and second bit line groups, respectively, depending on memory operating mode.

    FRACTION-N DIGITAL PLL CAPABLE OF CANCELING QUANTIZATION NOISE FROM SIGMA-DELTA MODULATOR
    277.
    发明申请
    FRACTION-N DIGITAL PLL CAPABLE OF CANCELING QUANTIZATION NOISE FROM SIGMA-DELTA MODULATOR 审中-公开

    公开(公告)号：US20180287620A1

    公开(公告)日：2018-10-04

    申请号：US15471483

    申请日：2017-03-28

    Applicant: STMicroelectronics International N.V.

    Inventor： Gagan Midha ,  Kallol Chatterjee

    IPC: H03L7/093 ,  H03M3/00 ,  H03L7/081 ,  H03L7/08

    Abstract: A phase locked loop (PLL) circuit disclosed herein includes a phase detector receiving a reference frequency signal and a feedback frequency signal, and configured to output a digital signal indicative of a phase difference between the reference frequency signal and the feedback frequency signal. A digital loop filter filters the digital signal. A digital to analog converter converts the filtered digital signal to a control signal. An oscillator generates a PLL clock signal based on the control signal. A sigma-delta modulator modulates a divider signal as a function of a frequency control word. A divider divides the PLL clock signal based on the divider signal, and generates a noisy feedback frequency signal based thereupon. A noise filtering block removes quantization noise from the noisy feedback frequency signal to thereby generate the feedback frequency signal.

    IMAGE SENSOR DEVICE WITH MACROPIXEL PROCESSING AND RELATED DEVICES AND METHODS
    279.
    发明申请
    IMAGE SENSOR DEVICE WITH MACROPIXEL PROCESSING AND RELATED DEVICES AND METHODS 审中-公开

    公开(公告)号：US20180241975A1

    公开(公告)日：2018-08-23

    申请号：US15958244

    申请日：2018-04-20

    Applicant: STMicroelectronics International N.V.

    Inventor： Mahesh Chandra ,  Brejesh Lall

    IPC: H04N9/04 ,  H04N5/347

    CPC classification number: H04N9/045 ,  H04N5/347

    Abstract: An image sensor device may include an array of image sensing pixels with adjacent image sensing pixels being arranged in macropixel, and a processor coupled to the array of image sensing pixels. The processor may be configured to receive pixel signals from the array of image sensing pixels, and arrange the received pixel signals into macropixel signal sets for respective macropixels. The processor may be configured to perform, in parallel, an image enhancement operation on the received pixel signals for each macropixel signal set to generate enhanced macropixel signals, and transmit the enhanced macropixel signals.

    Polyphase decimation FIR filters and methods
    280.
    发明授权
    Polyphase decimation FIR filters and methods 有权

    公开(公告)号：US10050607B2

    公开(公告)日：2018-08-14

    申请号：US14573055

    申请日：2014-12-17

    Applicant: STMicroelectronics International N.V.

    Inventor： Neha Bhargava ,  Ankur Bal

    IPC: H03H17/06 ,  H03H17/02

    Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.

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