公开(公告)号：US6005727A

公开(公告)日：1999-12-21

申请号：US790038

申请日：1997-01-28

Applicant: Richard T. Behrens ,  Christopher P. Zook ,  David E. Reed ,  Stephen A. Turk

Inventor： Richard T. Behrens ,  Christopher P. Zook ,  David E. Reed ,  Stephen A. Turk

IPC: G11B5/55 ,  G11B5/596 ,  G11B7/007 ,  G11B21/08 ,  G11B21/10 ,  G11B27/30 ,  G11B5/09

CPC classification number: G11B7/00745 ,  G11B21/083 ,  G11B21/106 ,  G11B27/3027 ,  G11B5/553 ,  G11B5/59655 ,  G11B5/59688 ,  G11B5/5547

Abstract: A servo decoder is disclosed for disc storage systems that operates according to a novel coding scheme capable of accurately decoding detected codewords representing servo track address during seek operations, even when the recording head flies between two adjacent tracks, and capable of correcting errors in the detected codedwords caused by noise in the read signal, such as inter-symbol interference. In a first embodiment, the coding scheme comprises an error correcting code (ECC) capable of correcting a predetermined number of bit errors in the detected codewords. To achieve the equivalent effect of a conventional Gray code, the codewords are arranged such that adjacent track addresses differ by a number of bits equal to the minimum distance of the ECC code. In a second embodiment, the servo code corrects certain minimum distance error events associated with a trellis type sequence detector. To achieve the equivalent effect of a conventional Gray code in this embodiment, the codewords are arranged such that adjacent track addresses differ by a number of bits relative to the minimum distance error events corrected. In this manner, when the recording head spans two adjacent tracks during a seek operation, the ambiguity in the detected codeword will be resolved in favor of one of the adjacent track addresses. Further, due to the error correcting capabilities of the code, the present invention improves the performance of servo seeking and tracking operations, and allows the servo data to be recorded at a higher density.

Abstract translation: 公开了一种用于盘存储系统的伺服解码器，该盘存储系统根据能够在搜索操作期间精确地解码表示伺服轨迹地址的检测码字的新型编码方案进行操作，即使当记录头在两个相邻的轨道之间飞行时，也能够校正检测到的错误 读取信号中由噪声引起的编码字，如符号间干扰。 在第一实施例中，编码方案包括能够校正检测码字中预定数量的位错误的纠错码（ECC）。 为了实现常规格雷码的等效效果，码字被布置成使得相邻轨道地址与等于ECC码的最小距离的位数相差。 在第二实施例中，伺服代码校正与网格型序列检测器相关联的某些最小距离误差事件。 为了实现本实施例中常规格雷码的等效效果，码字被布置成使得相邻轨道地址相对于校正的最小距离误差事件相差多个位。 以这种方式，当在搜索操作期间记录头跨越两个相邻轨道时，检测到的码字中的模糊度将被解析为有利于相邻轨道地址之一。 此外，由于代码的纠错能力，本发明提高了伺服寻找和跟踪操作的性能，并允许以更高的密度记录伺服数据。

公开(公告)号：US5999355A

公开(公告)日：1999-12-07

申请号：US640410

申请日：1996-04-30

Applicant: Richard T. Behrens ,  William G. Bliss ,  Li Du ,  Mark S. Spurbeck ,  German S. Feyh ,  Trent O. Dudley

Inventor： Richard T. Behrens ,  William G. Bliss ,  Li Du ,  Mark S. Spurbeck ,  German S. Feyh ,  Trent O. Dudley

IPC: G11B5/012 ,  G11B5/035 ,  G11B5/09 ,  G11B20/10 ,  G11B20/14 ,  G11B20/18 ,  H03H15/00 ,  H03H17/02 ,  H03H17/06 ,  H04L7/00 ,  H04L7/02 ,  H04L25/03

CPC classification number: G11B20/10055 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/1403 ,  G11B5/09 ,  G11B5/012 ,  G11B5/035 ,  H04L7/0029 ,  H04L7/0062

Abstract: A sampled amplitude read channel for magnetic disk recording which asynchronously samples the analog read signal, adaptively equalizes the resulting discrete time sample values according to a target partial response, extracts synchronous sample values through interpolated timing recovery, and detects digital data from the synchronous sample values using a Viterbi sequence detector is disclosed. To minimize interference from the timing and gain control loops, the phase and magnitude response of the adaptive equalizer filter are constrained at a predetermined frequency using an optimal orthogonal projection operation as a modification to a least mean square (LMS) adaptation algorithm. Further, with interpolated timing recovery, the equalizer filter and its associated latency are removed from the timing recovery loop, thereby allowing a higher order discrete time filter and a lower order analog filter.

Abstract translation: 用于磁盘记录的采样幅度读取通道，其异步采样模拟读取信号，根据目标部分响应对所得离散时间采样值进行自适应均衡，通过内插定时恢复提取同步采样值，并从同步采样值检测数字数据 公开了使用维特比序列检测器。 为了最小化来自定时和增益控制环路的干扰，使用最佳正交投影操作将自适应均衡器滤波器的相位和幅度响应约束在预定频率，作为对最小均方（LMS）适配算法的修改。 此外，通过内插定时恢复，均衡器滤波器及其相关等待时间从定时恢复环路中移除，从而允许较高阶离散时间滤波器和较低阶模拟滤波器。

公开(公告)号：US05999200A

公开(公告)日：1999-12-07

申请号：US12333

申请日：1998-01-23

Applicant: Patrick A. Harkin ,  Michael K. Larson

Inventor： Patrick A. Harkin ,  Michael K. Larson

IPC: G06F9/312 ,  G06F9/38 ,  G06F15/00

CPC classification number: G06F9/3877 ,  G06F9/30043

Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes a command address feed logic device decodes the display list to determine the register locations in a register file to fill with data. The command address feed logic device decodes the display list and orders a group of registers in the register file in order to perform a sequential write to the register file. By sequentially ordering the register file locations, the command address feed logic device is able to write null or zero data values to the register locations which are not needed to render a primitive, while maintaining a single write cycle to the register file.

Abstract translation: 图形系统包括用于使用显示参数列表来渲染图形基元的图形处理器。 主机处理器生成包括用于渲染图形基元的XY地址的显示列表。 包括命令地址馈送逻辑设备的图形处理器对显示列表进行解码以确定寄存器文件中的寄存器位置以填充数据。 命令地址馈送逻辑器件对显示列表进行解码，并对寄存器文件中的一组寄存器进行排序，以便对寄存器文件进行顺序写入。 通过顺序排序寄存器文件位置，命令地址馈送逻辑器件能够将零或零数据值写入到不需要渲染原语的寄存器位置，同时保持对寄存器文件的单个写周期。

公开(公告)号：US5999199A

公开(公告)日：1999-12-07

申请号：US968502

申请日：1997-11-12

Applicant: Michael K. Larson

Inventor： Michael K. Larson

IPC: G06T1/60 ,  G06T15/00 ,  G06F13/16

CPC classification number: G06T1/60 ,  G06T15/005

Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes internal fetch and store static random access memory (SRAM)devices for storing pixel fetched from an external memory device and processed in the graphics processor respectively. The graphics processor also includes a memory control logic which determines whether fetch and store requests by the graphics processor crosses an X boundary in the internal SRAM devices. If a fetch or store request crosses an X boundary, the memory control logic divides the access into two separate accesses which are then non-sequentially accessed during a single data request cycle. By non-sequentially fetching and storing data, the graphics processor is able to execute a single X crossing for multiple Y scan-line operations to fetch or store data internally.

Abstract translation: 图形系统包括用于使用显示参数列表来渲染图形基元的图形处理器。 主机处理器生成包括用于渲染图形基元的XY地址的显示列表。 一种图形处理器，其包括内部获取和存储静态随机存取存储器（SRAM）器件，用于存储从外部存储器件获取并分别在图形处理器中处理的像素。 图形处理器还包括存储器控制逻辑，其确定图形处理器的读取和存储请求是否跨越内部SRAM器件中的X边界。 如果获取或存储请求跨越X边界，则存储器控制逻辑将访问划分为两个单独的访问，然后在单个数据请求周期期间非访问该访问。 通过非顺序地取出和存储数据，图形处理器能够执行多个Y扫描线操作的单个X交叉以在内部获取或存储数据。

公开(公告)号：US5991911A

公开(公告)日：1999-11-23

申请号：US970600

申请日：1997-11-14

Applicant: Christopher P. Zook

Inventor： Christopher P. Zook

IPC: G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  H03M13/15 ,  H03M13/29

CPC classification number: H03M13/093 ,  G11B20/1833 ,  H03M13/1515 ,  H03M13/29 ,  H03M13/2909 ,  G11B20/18

Abstract: A compact disk (CD) and digital video disk (DVD) error correction system is disclosed which generates a CRC validation syndrome on-the-fly while correcting the CD/DVD product code, thereby reducing the overall access latency as compared to the prior art. For the DVD product code, which comprises multiple data sectors with separate CRC symbols appended to each data sector, a buffer used for C1 and C2 encoding/decoding in CD mode is used to store partial data and error CRC syndromes for each data sector. During the vertical (P) and horizontal (Q) passes over the DVD product code, data and error CRC syndrome registers are loaded with the appropriate partial CRC syndromes depending on the current data symbol being processed by a P/Q decoder. After processing each data sector, the data and error CRC syndromes for each data sector are combined and compared to a constant to determine whether the corrections to the data sector are valid and complete. The data and error CRC syndromes are adjusted during the P and Q passes to account for offsets in the CRC codeword symbols. For example, when processing a vertical (i.e., P) codeword, it is necessary to adjust the error CRC syndromes by one row of data symbols for each vertical symbol processed. This is carried out by using a special multiplier circuit which multiplies the data and error CRC syndromes byx.sup.k MODG(x)where k is the offset (e.g., one row of symbols) and G(x) is the CRC generator polynomial.

Abstract translation: 公开了一种紧凑盘（CD）和数字视盘（DVD）纠错系统，其在校正CD / DVD产品代码的同时产生CRC验证综合征，从而与现有技术相比降低了总体访问等待时间 。 对于DVD产品代码，其包括具有附加到每个数据扇区的单独的CRC符号的多个数据扇区，用于CD模式的C1和C2编码/解码的缓冲器用于存储针对每个数据扇区的部分数据和错误CRC校验子。 在垂直（P）和水平（Q）中通过DVD产品代码时，根据由P / Q解码器处理的当前数据符号，数据和错误CRC校验寄存器被加载适当的部分CRC校验子。 在处理每个数据扇区之后，将每个数据扇区的数据和错误CRC校验子组合，并将其与常数进行比较，以确定对数据扇区的校正是否有效和完整。 在P和Q传递期间调整数据和错误CRC校验子以考虑CRC码字符号中的偏移量。 例如，当处理垂直（即，P）码字时，需要为处理的每个垂直符号调整错误CRC校正子一行数据符号。 这通过使用将数据和错误CRC校验子乘以xkMODG（x）的特殊乘法器电路来执行，其中k是偏移量（例如，一行符号），G（x）是CRC生成器多项式。

公开(公告)号：US5986830A

公开(公告)日：1999-11-16

申请号：US902832

申请日：1997-07-30

Applicant: Jerrell P. Hein

Inventor： Jerrell P. Hein

IPC: G11B5/012 ,  G11B5/035 ,  G11B20/10 ,  G11B20/14 ,  G11B5/09

CPC classification number: G11B20/1403 ,  G11B20/10009 ,  G11B5/035 ,  G11B5/012

Abstract: An improved write precompensation circuit for a read/write channel circuit and system is provided. Multiple data input signals are provided, each being clocked by a different clock. The data input signals are then multiplexed. Two, three or more data clock delays may be utilized to provide two, three or more data delays to achieve the write precompensation. Only one edge of a signal need pass through a multiplexer before the multiplexer may change state. The amount of delay may be user programmable.

Abstract translation: 提供了一种用于读/写通道电路和系统的改进的预预补偿电路。 提供了多个数据输入信号，每个数据输入信号由不同的时钟计时。 然后数据输入信号被复用。 可以使用两个，三个或更多个数据时钟延迟来提供两个，三个或更多个数据延迟以实现写入预补偿。 在多路复用器可能改变状态之前，信号的仅一个边缘需要通过多路复用器。 延迟量可能是用户可编程的。

公开(公告)号：US5986663A

公开(公告)日：1999-11-16

申请号：US948626

申请日：1997-10-10

Applicant: Daniel P. Wilde

Inventor： Daniel P. Wilde

IPC: G06T15/04 ,  G06T15/00

CPC classification number: G06T15/04

Abstract: A graphics system includes a graphics controller for rendering polygons with texture using an improved MIP mapping technique. The graphics controller includes a polygon engine for rendering the pixels in a polygon and a texture map engine for selecting texture elements ("texels") from an appropriate texture map to be applied to the pixels rendered by the polygon engine. The texture map engine generates texel coordinate values from pixel coordinate values provided by the polygon engine. The appropriate texture map is selected from a set of texture maps each varying from the others by the level of detail of the texture in each map. The graphics controller selects the appropriate level of detail texture map to use to increase speed, efficiency, and realism quality of the graphics system. The determination as to which level of detail texture map is appropriate is made by computing the area bounded by adjacent texel coordinates generated by the texture map engine. In the preferred embodiment, vectors are defined for each the adjacent texels and the area is determined from the magnitude of the cross product of the vectors.

Abstract translation: 图形系统包括用于使用改进的MIP映射技术来渲染具有纹理的多边形的图形控制器。 图形控制器包括用于渲染多边形中的像素的多边形引擎和用于从适当的纹理图选择纹理元素（“纹理”）的纹理映射引擎，以将其应用于由多边形引擎呈现的像素。 纹理映射引擎从由多边形引擎提供的像素坐标值生成纹素坐标值。 从一组纹理贴图中选择适当的纹理贴图，每个纹理贴图通过每个贴图中纹理的细节级别而不同。 图形控制器选择适当的细节纹理图层来提高图形系统的速度，效率和现实质量。 通过计算由纹理映射引擎生成的相邻纹素坐标所限定的区域来确定哪个级别的细节纹理图是适当的。 在优选实施例中，针对每个相邻纹理像素定义矢量，并且根据矢量的十字积的大小来确定该区域。

公开(公告)号：US5982690A

公开(公告)日：1999-11-09

申请号：US60932

申请日：1998-04-15

Applicant: James D. Austin

Inventor： James D. Austin

IPC: G11C7/06 ,  G11C7/00

CPC classification number: G11C7/065

Abstract: A static, low-power differential sense amplifier (DSA) and method includes operation of cross-linked channels having complementary differential nodes separated from ground by corresponding parallel-transistor pairs. The DSA output channels have complementary output nodes separated from ground by corresponding parallel-transistor pairs. The DSA further includes logic gates to produce a sense amplifier output. Each logic gate is driven by a corresponding complementary differential node and an opposite complimentary output node. The DSA includes transistors activating a done line under control of the complementary differential nodes.

Abstract translation: 静态，低功率差分读出放大器（DSA）和方法包括具有通过对应的并联 - 晶体管对与地分离的互补差分节点的交联通道的操作。 DSA输出通道具有通过相应的并联 - 晶体管对与地分离的互补输出节点。 DSA还包括产生读出放大器输出的逻辑门。 每个逻辑门由相应的互补差分节点和相对的互补输出节点驱动。 DSA包括在互补差分节点的控制下激活完成线的晶体管。

公开(公告)号：US5956304A

公开(公告)日：1999-09-21

申请号：US912916

申请日：1997-08-15

Applicant: Louis Supino ,  Paul M. Romano ,  Larry D. King ,  German S. Feyh

Inventor： Louis Supino ,  Paul M. Romano ,  Larry D. King ,  German S. Feyh

IPC: G11B7/085 ,  G11B7/09 ,  G11B7/00

CPC classification number: G11B7/0906 ,  G11B7/08541 ,  G11B7/0901

Abstract: In an optical disk storage device, a differential phase detector is disclosed for generating a position error signal independent of the frequency content of the recorded data. A pair if diagonal signals S1 and S2 are generated by adding a pair of respective quadrants of a four-quadrant photodetector, where the phase offset between the diagonal signals represents the position error of the pit image as it passes over the photodetector. The position error is determined in the present invention by computing the difference between a positive and negative correlation of the diagonal signals S1 and S2, otherwise referred to as a dual arm correlation (DAC) ##EQU1## where .DELTA. is the correlation offset and L is the correlation length. In the preferred embodiment, the correlation offset .DELTA. is adaptively adjusted to maximize the correlation between S1 and S2. In this manner, the position error estimate is substantially insensitive to the frequency content of the recorded data. Furthermore, this method extends the position error over a range of plus or minus one-half a track, which facilitates generating a quadrature signal for use in counting track crossings during seek operations.

Abstract translation: 在光盘存储装置中，公开了用于产生与记录数据的频率内容无关的位置误差信号的差分相位检测器。 如果对角线信号S1和S2是通过增加四象限光电检测器的一对相应象限来产生的，其中对角线信号之间的相位偏移表示当其通过光电检测器时凹坑图像的位置误差。 在本发明中通过计算对角线信号S1和S2的正相关和负相关之间的差异来确定位置误差，否则称为双相位相关（DAC），其中DELTA是相关偏移，L是相关长度 。 在优选实施例中，相关偏移量DELTA被自适应地调整以最大化S1和S2之间的相关性。 以这种方式，位置误差估计对记录数据的频率内容基本不敏感。 此外，该方法将位置误差扩展到正或负二分之一的轨道的范围，这有利于产生用于在搜索操作期间计数轨道交叉的正交信号。

公开(公告)号：US5924183A

公开(公告)日：1999-07-20

申请号：US846932

申请日：1997-04-29

Applicant: Mark P. Kelley ,  Yakov A. Bobrov

Inventor： Mark P. Kelley ,  Yakov A. Bobrov

IPC: B21K23/00 ,  G01R31/02

CPC classification number: G01R31/2893 ,  Y10T29/49716 ,  Y10T29/49963

Abstract: A method of adapting a hand test socket for use in a workpress assembly includes: providing a hand test socket having a base and a top cover. The top cover includes a clamp. The method includes the step: removing the top cover and the clamp and configuring the clamp for use in a workpress assembly. The step of configuring the clamp includes forming a frame and attaching the clamp to the frame.

Abstract translation: 一种适应用于工作压力组件的手测试插座的方法包括：提供具有底座和顶盖的手测试插座。 顶盖包括夹具。 该方法包括以下步骤：拆下顶盖和夹具并配置夹具以用于工作压力组件。 构造夹具的步骤包括形成框架并将夹具附接到框架。