公开(公告)号：US07096485B2

公开(公告)日：2006-08-22

申请号：US10037305

申请日：2001-12-21

Applicant: Pascal Voyer ,  Marc Mondeteguy

Inventor： Pascal Voyer ,  Marc Mondeteguy

IPC: G06F13/00

CPC classification number: H04N21/4332 ,  H04N7/0884 ,  H04N21/4532 ,  H04N21/84

Abstract: The method of filtering data concerning an electronic program guide (EPG) in a television receiver having a device for automatically searching television channels includes supplying a list of CNI codes of all or some of the channels received by the television receiver to a memory. The method includes obtaining, from the SUMMARY of the guide, a MODIFIED SUMMARY containing only the information of the SUMMARY concerning all or some of the channels received by the television receiver, and recording only the data blocks of the CONTENTS of the guide in a memory when they correspond to all or some of the channels received by the television receiver.

Abstract translation: 在具有用于自动搜索电视频道的设备的电视接收机中过滤关于电子节目指南（EPG）的数据的方法包括将由电视接收机接收的全部或一些频道的CNI码列表提供给存储器。 该方法包括从引用的摘要中获得一个仅包含关于由电视接收机接收的全部或一些频道的发明内容的信息的修改摘要，并且仅将指南的内容的数据块仅记录在存储器中 当它们对应于电视接收机接收的全部或一些频道时。

公开(公告)号：US20060139109A1

公开(公告)日：2006-06-29

申请号：US11235787

申请日：2005-09-27

Applicant: Alain Oustaloup ,  Yann Deval ,  Didier Belot ,  Pierre Melchior ,  Jean-Baptiste Begueret ,  Franck Badets ,  Vincent Lagareste

Inventor： Alain Oustaloup ,  Yann Deval ,  Didier Belot ,  Pierre Melchior ,  Jean-Baptiste Begueret ,  Franck Badets ,  Vincent Lagareste

IPC: H03L7/00

CPC classification number: H03L7/093 ,  H03H7/06 ,  H03L7/0891 ,  H03L7/18

Abstract: The frequency synthesizer includes a phase-locked loop (PLL). The PLL includes an oscillator controlled to deliver an output signal at a predefined output frequency, a variable frequency divider to convert the output signal into a divided-frequency signal, a phase comparator to produce a signal measuring a phase difference between the divided-frequency signal and a reference signal at a reference frequency, and a loop filter to control the oscillator on the basis of the measurement signal. To increase the speed of convergence of the synthesizer if the set point is changed, the loop filter of the PLL is a fractional, i.e. non-integer, order low-pass filter.

Abstract translation: 频率合成器包括锁相环（PLL）。 PLL包括被控制以以预定的输出频率传送输出信号的振荡器，用于将输出信号转换成分频信号的可变分频器，相位比较器，以产生测量分频信号之间的相位差的信号 以及参考频率的参考信号，以及环路滤波器，用于根据测量信号控制振荡器。 为了增加合成器的收敛速度，如果设定点改变，PLL的环路滤波器是分数即非整数阶低通滤波器。

公开(公告)号：US20060138636A1

公开(公告)日：2006-06-29

申请号：US11305886

申请日：2005-12-16

Applicant: Pierre Bormann ,  Luc Morineau ,  Jacques Chavade

Inventor： Pierre Bormann ,  Luc Morineau ,  Jacques Chavade

IPC: H01L23/52

CPC classification number: H01L23/49838 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K1/114 ,  H05K2201/09227 ,  H05K2201/10734

Abstract: A device is provided for electrically connecting an integrated circuit chip. The device includes a main board, an intermediate board, and electrical connection balls in a space separating the boards. In the space, a peripheral zone comprises a peripheral matrix of balls, a central zone comprises a central matrix of balls, a first secondary zone comprises a matrix of electrical connection vias linked to the balls of the two adjacent rows of balls of the peripheral matrix, and a second secondary zone comprises a matrix of electrical connection vias linked to balls of the central matrix. The first secondary zone and the second secondary zone are separated by an intermediate zone that includes at least a first part having at least one complementary row of electrical connection balls, and a second part having complementary electrical connection vias linked to the balls of this complementary row.

公开(公告)号：US07069404B1

公开(公告)日：2006-06-27

申请号：US09479105

申请日：2000-01-07

Applicant: Franck Roche

Inventor： Franck Roche

IPC: G06F12/00

CPC classification number: G06F12/1433

Abstract: A microprocessor is provided with protection circuits to secure access to its registers. The microprocessor includes a plurality of protection circuits, each associated with a register of the microprocessor. The protection circuits automatically block selection of the registers after each resetting of the microprocessor. The releasing of a protection circuit associated with a register is done by the successive sending, on the data bus, of N passwords proper to the register during N first operations for the selection of the register with N≧1. The selection of the register is effective only for the subsequent operations for selection of the register up to the next resetting of the microprocessor.

Abstract translation: 微处理器提供有保护电路以确保访问其寄存器。 微处理器包括多个保护电路，每个保护电路与微处理器的寄存器相关联。 每个微处理器复位后，保护电路会自动阻止寄存器的选择。 与寄存器相关联的保护电路的释放是通过在数据总线上连续发送N个第一个操作中适合于N个密码的N个密码进行的，以选择N> = 1的寄存器。 寄存器的选择只对后续的寄存器选择操作有效，直到微处理器的下一次复位。

公开(公告)号：US07064061B2

公开(公告)日：2006-06-20

申请号：US10466828

申请日：2002-01-17

Applicant: Gérard Passemard ,  Emmanuel Sicurani ,  Charles Lecornec

Inventor： Gérard Passemard ,  Emmanuel Sicurani ,  Charles Lecornec

IPC: H01L21/4763

CPC classification number: H01L21/76831 ,  H01L21/76807

Abstract: The process includes depositing a filling material in trenches formed in at least one layer of dielectric so as to fill open pores in the dielectric. The filling material is intended to prevent the subsequent diffusion of the interconnect metal and/or of a metal of a diffusion barrier, and may be non-porous. The filling material preferably has a low dielectric constant.

Abstract translation: 该方法包括在形成在至少一层电介质中的沟槽中沉积填充材料，以填充电介质中的开孔。 填充材料旨在防止互连金属和/或扩散阻挡层的金属的后续扩散，并且可以是非多孔的。 填充材料优选具有低介电常数。

公开(公告)号：US20060057782A1

公开(公告)日：2006-03-16

申请号：US11213098

申请日：2005-08-26

Applicant: Pascal Gardes ,  Fabrice Guitton

Inventor： Pascal Gardes ,  Fabrice Guitton

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC classification number: H01L21/6836 ,  H01L21/6835 ,  H01L21/78 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2224/0401

Abstract: The manufacturing of electronic components on individual substrates made of an insulating material includes molding, in a silicon wafer, an insulating material with a thickness corresponding to the final thickness desired for the substrates, manufacturing the electronic components, and removing the silicon from the rear surface of the wafer after manufacturing of the components.

公开(公告)号：US20060020719A1

公开(公告)日：2006-01-26

申请号：US11179033

申请日：2005-07-11

Applicant: Albert Martinez ,  Jean Nicolai

Inventor： Albert Martinez ,  Jean Nicolai

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F12/1081

Abstract: A method for programming a DMA controller of a system on a chip that includes a CPU, an MMU, and a DMA controller including source, destination, and size registers associated with a base subaddress. In response to a first instruction of a user program that includes a virtual address, the virtual address is translated into a corresponding physical address, and the physical address is stored in a buffer register that is inaccessible to the user program. In response to a second instruction of the user program, the physical address stored in the buffer register is applied to the data bus and a first word including high-order bits indicating the base subaddress is applied to the address bus. The source or destination register is selected according to the first word applied to the address bus and the physical address applied to the data bus is stored in the selected register.

Abstract translation: 一种用于对包括CPU，MMU和DMA控制器的芯片上的系统的DMA控制器进行编程的方法，包括与基本子地址相关联的源，目的地和大小寄存器。 响应于包括虚拟地址的用户程序的第一指令，虚拟地址被转换成对应的物理地址，物理地址存储在用户程序不可访问的缓冲寄存器中。 响应于用户程序的第二指令，存储在缓冲寄存器中的物理地址被施加到数据总线，并且包括指示基本子地址的高位的第一个字被施加到地址总线。 源或目标寄存器根据应用于地址总线的第一个字来选择，并且应用于数据总线的物理地址存储在所选择的寄存器中。

公开(公告)号：US06989310B2

公开(公告)日：2006-01-24

申请号：US10689528

申请日：2003-10-20

Applicant: Yvon Gris

Inventor： Yvon Gris

IPC: H01L21/20

CPC classification number: H01L28/20 ,  H01L27/0802

Abstract: A process for selectively doping predetermined resistive elements on an electronic chip is provided. The resistive elements are arranged in a pattern, and there are three phases in the process. The first phase electrically charges selected elements of the pattern. The second phase adds doping atoms to the charged elements as a function of their state of charge. The third phase anneals the electronic chip to cause penetration of the doping agents and to activate them.

Abstract translation: 提供了用于在电子芯片上选择性地掺杂预定电阻元件的工艺。 电阻元件以图案布置，并且在该过程中存在三个阶段。 第一阶段对所选择的图案元素进行电荷充电。 第二阶段根据其充电状态将掺杂原子添加到带电元件。 第三阶段使电子芯片退火以引起掺杂剂的渗透并激活它们。

公开(公告)号：US20060007155A1

公开(公告)日：2006-01-12

申请号：US11171125

申请日：2005-06-30

Applicant: Jeffrey Raynor ,  Pascal Mellot

Inventor： Jeffrey Raynor ,  Pascal Mellot

IPC: G09G5/08

CPC classification number: G06F3/0317

Abstract: An optical mouse includes an image sensor for providing image data via an analog-to-digital converter to a correlation circuit and a motion estimation circuit to provide output signals representative of motion of the mouse. The output signals may be disabled when the mouse is lifted away from the working surface. This may be achieved by high-pass filtering the signals, summing each frame in a summer to provide a single value, and comparing this to a threshold. If the filtered and summed value exceeds the threshold, this may indicate that the image contains in-focus objects, and that the mouse is on the working surface.

公开(公告)号：US20060002191A1

公开(公告)日：2006-01-05

申请号：US11155012

申请日：2005-06-16

Applicant: Christophe Frey ,  David Turgis ,  Jean-Christophe Lafont

Inventor： Christophe Frey ,  David Turgis ,  Jean-Christophe Lafont

IPC: G11C11/34

CPC classification number: G11C11/412

Abstract: A memory cell (1), includes: a flip-flop (2) that has additional read/write terminals; a 1-bit write line (wb11); a first transistor (T4) switching between the 1-bit write line and the terminal, its gate being connected to a word selection line (W11); a 0-bit write line (wb10); a second transistor (T3) switching between the 0-bit write line and the terminal, its gate being connected to a word selection line (W12); a bit read line (b1r); and read transistors (T1, T2), with one of their gates being connected to a read/write terminal and the other being connected to a word selection line. The invention particularly allows the surface area and complexity of a memory cell to be reduced.

Abstract translation: 存储单元（1）包括：具有附加读/写端子的触发器（2）; 1位写入线（wb 11）; 第一晶体管（T 4）在1位写入线和端子之间切换，其栅极连接到字选择线（W 11）; 0位写行（wb 10）; 第二晶体管（T 3）在0位写入线和端子之间切换，其栅极连接到字选择线（W 12）; 读一行（b 1 r）; 并读取晶体管（T 1，T 2），其中一个栅极连接到读/写端子，另一个连接到字选择线。 本发明特别允许减小存储单元的表面积和复杂性。