公开(公告)号：US20240379800A1

公开(公告)日：2024-11-14

申请号：US18782176

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Yi-Tse Hung ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li ,  Jin Cai

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

公开(公告)号：US20240379797A1

公开(公告)日：2024-11-14

申请号：US18781353

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Shahaji B. More ,  Yi-Ying Liu ,  Shuen-Shin Liang ,  Sung-Li Wang

IPC: H01L29/423 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: In an embodiment, a device includes: a first insulating fin; a second insulating fin; a nanostructure between the first insulating fin and the second insulating fin; and a gate structure wrapping around the nanostructure, a top surface of the gate structure disposed above a top surface of the first insulating fin, the top surface of the gate structure disposed below a top surface of the second insulating fin.

公开(公告)号：US20240379792A1

公开(公告)日：2024-11-14

申请号：US18782840

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Eugene I-Chun Chen ,  Ru-Liang Lee ,  Chia-Shiung Tsai ,  Chen-Hao Chiang

IPC: H01L29/423 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: A method of forming a semiconductor device includes: forming an etch stop layer over a substrate; forming a first diffusion barrier layer over the etch stop layer; forming a semiconductor device layer over the first diffusion barrier layer, the semiconductor device layer including a transistor; forming a first interconnect structure over the semiconductor device layer at a front side of the semiconductor device layer, the first interconnect structure electrically coupled to the transistor; attaching the first interconnect structure to a carrier; removing the substrate, the etch stop layer, and the first diffusion barrier layer after the attaching; and forming a second interconnect structure at a backside of the semiconductor device layer after the removing.

公开(公告)号：US20240379781A1

公开(公告)日：2024-11-14

申请号：US18780151

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Hao Lu ,  Li-Li Su ,  Chien-I Kuo ,  Yee-Chia Yeo ,  Wei-Yang Lee ,  Yu-Xuan Huang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/417 ,  H01L21/02 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device, includes a device layer comprising: a channel region; a gate stack over and along sidewalls of the channel region and a first insulating fin; and an epitaxial source/drain region adjacent the channel region, wherein the epitaxial source/drain region extends through the first insulating fin. The semiconductor device further includes a front-side interconnect structure on a first side of the device layer; and a backside interconnect structure on a second side of the device layer opposite the first side of the device layer. The backside interconnect structure comprises a backside source/drain contact that is electrically connected to the epitaxial source/drain region.

公开(公告)号：US20240379777A1

公开(公告)日：2024-11-14

申请号：US18783848

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui ,  Chun-I Wu ,  Huang-Lin Chao

IPC: H01L29/40 ,  H01L21/28 ,  H01L21/285 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, depositing a metal-containing layer over the gate dielectric layer, and depositing a silicon-containing layer on the metal-containing layer. The metal-containing layer and the silicon-containing layer in combination act as a work-function layer. A planarization process is performed to remove excess portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer, with remaining portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer forming a gate stack.

公开(公告)号：US20240379762A1

公开(公告)日：2024-11-14

申请号：US18779804

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Chun-An Lin ,  Wei-Yuan Lu ,  Guan-Ren Wang ,  Peng Wang

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

公开(公告)号：US20240379750A1

公开(公告)日：2024-11-14

申请号：US18775808

申请日：2024-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Guan-Lin Chen ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Jung-Chien Cheng ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure comprises a fin and a layer stack overlying the fin, where the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin structure; forming openings in the fin structure on opposing sides of the dummy gate structure, where the openings extend through the layer stack into the fin; forming a dielectric layer in bottom portions of the openings; and forming source/drain regions in the openings on the dielectric layer, where the source/drain regions are separated from the fin by the dielectric layer.

公开(公告)号：US20240379682A1

公开(公告)日：2024-11-14

申请号：US18784484

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Chandrashekhar Prakash Savant

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: In an embodiment, a device includes: a first fin extending from a substrate; a second fin extending from the substrate; a gate spacer over the first fin and the second fin; a gate dielectric having a first portion, a second portion, and a third portion, the first portion extending along a first sidewall of the first fin, the second portion extending along a second sidewall of the second fin, the third portion extending along a third sidewall of the gate spacer, the third portion and the first portion forming a first acute angle, the third portion and the second portion forming a second acute angle; and a gate electrode on the gate dielectric.

公开(公告)号：US20240379680A1

公开(公告)日：2024-11-14

申请号：US18779905

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L27/092 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate, the gate structure being surrounded by a first interlayer dielectric (ILD) layer; forming a trench in the first ILD layer adjacent to the fin; filling the trench with a first dummy material; forming a second ILD layer over the first ILD layer and the first dummy material; forming an opening in the first ILD layer and the second ILD layer, the opening exposing a sidewall of the first dummy material; lining sidewalls of the opening with a second dummy material; after the lining, forming a conductive material in the opening; after forming the conductive material, removing the first and the second dummy materials from the trench and the opening, respectively; and after the removing, sealing the opening and the trench by forming a dielectric layer over the second ILD layer.

公开(公告)号：US20240379678A1

公开(公告)日：2024-11-14

申请号：US18779675

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Shuan Li ,  Tsung-Lin Lee ,  Chih Chieh Yeh

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a number of channel members over a substrate, a gate structure wrapping around each of the number of channel members, a dielectric fin structure disposed adjacent to the gate structure, the dielectric fin structure includes a first dielectric layer disposed over the substrate and in direct contact with the first gate structure, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer. The third dielectric is disposed over the second dielectric layer and spaced apart from the first dielectric layer and the gate structure by the second dielectric layer. The dielectric fin structure also includes an isolation feature disposed directly over the third dielectric layer.