公开(公告)号：US12238273B2

公开(公告)日：2025-02-25

申请号：US17095765

申请日：2020-11-12

Applicant: MELLANOX TECHNOLOGIES, LTD. ,  BEAMR IMAGING LTD.

Inventor： Dotan David Levi ,  Assaf Weissman ,  Ohad Markus ,  Uri Gadot ,  Aviad Raveh ,  Dror Gill ,  Nikolay Terterov ,  Pavel Titkov ,  Alexey Mitkovets ,  Alexey Martemyanov ,  Alexander Zheludkov

IPC: H04N19/105 ,  H04N19/119 ,  H04N19/159 ,  H04N19/176 ,  H04N19/51

Abstract: A video coding system including an acceleration device including input circuitry configured, for each of a first plurality of video frames to be encoded, to receive an input including at least one raw video frame and at least one reference frame, and to divide each of the first plurality of video frames to be encoded into a second plurality of blocks, and similarity computation circuitry configured, for each one of the first plurality of video frame to be encoded: for each the block of the second plurality of blocks, to produce an intra-prediction hint and an intra-prediction direction. Related apparatus and methods are also provided.

公开(公告)号：US12224950B2

公开(公告)日：2025-02-11

申请号：US17979018

申请日：2022-11-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gal Yefet ,  Daniel Marcovitch ,  Roee Moyal ,  Gil Bloch ,  Ariel Shahar ,  Yossef Itigin

IPC: G06F15/16 ,  H04L47/62 ,  H04L47/625 ,  H04L47/6275

Abstract: In one embodiment, a system includes a memory to store a work queue including work queue entry slots, a processing device to write work queue entries to the work queue in a consecutive and cyclic manner, and a network device including a network interface to share packet over a network, and packet processing circuitry to read the work queue entries from the work queue in a consecutive and cyclic manner, the work queue entries indicating work to be performed associated with the packets, dequeue respective ones of the work queue entries read from the work queue responsively to reading the respective work queue entries from the work queue, add the work queue entries to an execution database used to track execution of the work queue entries, and execute the work queue entries in the execution database.

公开(公告)号：US20250044981A1

公开(公告)日：2025-02-06

申请号：US18229509

申请日：2023-08-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Niv Aibester ,  Eyal Srebro ,  Liron Mula ,  Amit Kazimirsky

IPC: G06F3/06

Abstract: A network device, a network interface controller, and a switch are provided. In one example, a shared buffer includes a plurality of cells of memory, one or more ports read data from the shared buffer and write data to the shared buffer, and a controller circuit selectively enables and disables cells of memory of the shared buffer based on an amount of data stored in the shared buffer. Power consumption of the shared buffer is in proportion to a number of enabled cells of memory.

公开(公告)号：US12216580B1

公开(公告)日：2025-02-04

申请号：US18456536

申请日：2023-08-28

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Yaniv Strassberg ,  Guy Harel ,  Gabi Liron ,  Yuval Itkin

IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/14

Abstract: A peripheral device includes a processor, a memory interface, a host interface and a cache controller. The processor executes software code. The cache memory caches a portion of the software code. The memory interface communicates with a NVM storing a replica of the software code. The host interface communicates with hosts storing additional replicas of the software code. The cache controller is to determine whether each host is allocated for code fetching, to receive a request from the processor for a segment of the software code, when available in the cache memory to fetch the segment from the cache memory, when unavailable in the cache memory and at least one host is allocated, to fetch the segment from the hosts that are allocated, when unavailable in the cache memory and no host is allocated, to fetch the segment from the NVM, and to serve the fetched segment to the processor.

公开(公告)号：US20250028658A1

公开(公告)日：2025-01-23

申请号：US18224262

申请日：2023-07-20

Applicant: Mellanox Technologies, Ltd.

Inventor： Ortal Ben Moshe ,  Roee Moyal ,  Shay Aisman ,  Gil Bloch ,  Ariel Shahar ,  Roman Nudelman ,  Gil Kremer ,  Yossef Itigin ,  Lior Narkis

IPC: G06F13/16 ,  G06F9/54

Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and a packet processing circuitry operatively coupled to the network interface. The packet processing circuitry may receive, via the network interface, a message; retrieve, via a packet processing circuitry, a work queue element (WQE) index identifying a position of a WQE in a receive queue; determine that the message is associated with a small payload; process the message without consuming the WQE; receive, via the network interface, a subsequent message; and process the subsequent message using the WQE. In this way, the systems and methods describe herein reduce the latency in processing of the data packets.

公开(公告)号：US20250023705A1

公开(公告)日：2025-01-16

申请号：US18219895

申请日：2023-07-10

Applicant: Mellanox Technologies, Ltd.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Thomas Kernen

IPC: H04L7/00

Abstract: A network device includes control logic coupled to a receiver. The control logic detects an synchronization packet received via the receiver from a second network device over a network that is precision time protocol unaware. The control logic determines that a portion of the synchronization packet is asserted, indicating that the synchronization packet has incurred congestion traversing the network. The control logic adjusts, based on an assertion of the portion, a weight applied to timestamps associated with sending and receiving the synchronization packet in performing clock synchronization with the second network device.

公开(公告)号：US20250023668A1

公开(公告)日：2025-01-16

申请号：US18351544

申请日：2023-07-13

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Roee Moyal ,  Gil Kremer ,  Ortal Ben Moshe ,  Ariel Shahar

IPC: H04L1/1607 ,  H04L1/08 ,  H04L47/34

Abstract: In one embodiment, a first network device includes a host interface to receive messages from a host device, packet processing circuitry to send a batch of the messages to a second network device without waiting for an acknowledgement receipt from the second network device after sending each message, one message in the batch having a maximum message sequence number (MSN), receive a given acknowledgement receipt from the second network device indicating that all the messages in the batch have been received and including credit data indicating that there is no space in a receive work queue of the second network device for receiving an additional message, and send the additional message having an MSN greater than the maximum MSN to the second network device responsively to receiving the given acknowledgement receipt and based on the credit data indicating that there is no space in the receive work queue.

公开(公告)号：US20250020876A1

公开(公告)日：2025-01-16

申请号：US18897843

申请日：2024-09-26

Applicant: Mellanox Technologies, Ltd.

Inventor： Barak FREEDMAN ,  Henning LYSDAL ,  Amir SILBER ,  Nizan MEITAV

IPC: G02B6/42 ,  G02B6/30

Abstract: Various embodiments of silicon photonic (SiP) chips are provided that are configured for backside or frontside optical fiber coupling. An SiP chip includes a photonic integrated circuit formed on a first surface of a first substrate. The photonic integrated circuit includes at least one optical component and at least one coupling element. The at least one optical component is configured to propagate an optical signal therethrough in a waveguide propagation direction that is substantially parallel to a plane defined by the first surface. The at least one coupling element is configured to couple an optical signal propagating along an optical path transverse to the waveguide propagation direction into the at least one optical component to enable the backside or frontside coupling of an optical fiber to the SiP chip.

公开(公告)号：US20250016110A1

公开(公告)日：2025-01-09

申请号：US18890429

申请日：2024-09-19

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Barak Gafni ,  Aviv Kfir

IPC: H04L47/36

Abstract: Networking devices, systems, and methods are provided. In one example, a method includes receiving a packet at a networking device; evaluating the packet; based on the evaluation of the packet, truncating the packet from a first size to a second size that is smaller than the first size; and storing the truncated packet in a buffer prior to transmitting the truncated packet with the networking device.

公开(公告)号：US12192122B2

公开(公告)日：2025-01-07

申请号：US18581423

申请日：2024-02-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Niv Aibester ,  Barak Gafni

IPC: H04L49/103 ,  H04L45/122 ,  H04L47/30 ,  H04L49/9005 ,  H04L49/9047

Abstract: A device includes ports, a packet processor, and a memory management circuit. The ports communicate packets over a network. The packet processor processes the packets using queues. The memory management circuit maintains a shared buffer in a memory and adaptively allocates memory resources from the shared buffer to the queues, maintains in the memory, in addition to the shared buffer, a shared-reserve memory pool for use by the queues, identifies, among the queues, a queue that requires additional memory resources, the queue having an occupancy that is (i) above a current value of a dynamic threshold, rendering the queue ineligible for additional allocation from the shared buffer, and (ii) no more than a defined margin above the current value of the dynamic threshold, rendering the queue eligible for allocation from the shared-reserve memory pool, and allocates memory resources to the identified queue from the shared-reserve memory pool.