公开(公告)号：US09093150B2

公开(公告)日：2015-07-28

申请号：US14016224

申请日：2013-09-03

申请人： Vijay Karamcheti ,  Kumar Ganapathy

发明人： Vijay Karamcheti ,  Kumar Ganapathy

IPC分类号： G11C16/04 ,  G06F12/06 ,  G06F17/30 ,  G06F12/02

CPC分类号： G11C16/0408 ,  G06F7/78 ,  G06F12/0207 ,  G06F12/0246 ,  G06F12/0607 ,  G06F17/30477 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C16/06 ,  Y02D10/13

摘要： A multi-chip packaged integrated circuit part for mounting to a printed circuit board of a memory module. The multi-chip packaged integrated circuit part comprises an integrated circuit package including a slave memory controller (SMC) die; and pairs of a spacer under the slave memory controller die, and a flash memory die under the spacer. In each pair, the flash memory die may be larger than the spacer so that an opening is provided into a perimeter of the flash memory die to allow electrical connections to be made. A plurality of conductors may be used to electrically couple the slave memory controller die and the flash memory die to one or more pads of a pin-out of the integrated circuit package.

摘要翻译： 一种用于安装到存储器模块的印刷电路板的多芯片封装集成电路部件。 多芯片封装集成电路部分包括集成电路封装，其包括从存储器控制器（SMC）管芯; 以及在从存储器控制器管芯之下的间隔物对，以及在间隔件下的闪存管芯。 在每对中，闪存芯片可以大于间隔件，使得开口设置在闪存芯片的周边中，以允许进行电连接。 可以使用多个导体来将从存储器控制器管芯和闪存管芯电耦合到集成电路封装的引脚输出的一个或多个焊盘。

公开(公告)号：US09021188B1

公开(公告)日：2015-04-28

申请号：US13843511

申请日：2013-03-15

申请人： Virident Systems Inc.

发明人： Vijay Karamcheti ,  Ashish Singhai ,  Shibabrata Mondal ,  Swamy Gowda

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F12/02

CPC分类号： G06F3/0608 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1012 ,  G06F11/1451 ,  G06F11/2058 ,  G06F12/0246 ,  G06F12/0646 ,  G06F12/121 ,  G06F2201/84 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/7202 ,  G06F2212/7203

摘要： A first portion of an asymmetric memory is configured as temporary storage for application data units with sizes corresponding to a small memory block that is smaller than the size of a logical write unit associated with the asymmetric memory. A portion of the remaining asymmetric memory is configured as a reconciled storage for application data units with varying sizes. A first application data unit is received for writing to the asymmetric memory. Based on computing the size of the first application data unit as corresponding to the small memory block, the first application data unit is written to the temporary storage. Upon determining that a threshold is reached, a memory write operation is performed for writing the application data units from the temporary storage to the reconciled storage. The application data units written to the reconciled storage are removed from the temporary storage.

公开(公告)号：US08706932B1

公开(公告)日：2014-04-22

申请号：US13163544

申请日：2011-06-17

申请人： Ruban Kanapathippillai ,  Ashwin Narasimha ,  Kenneth A. Okin ,  Vijay Karamcheti

发明人： Ruban Kanapathippillai ,  Ashwin Narasimha ,  Kenneth A. Okin ,  Vijay Karamcheti

IPC分类号： G06F13/12

CPC分类号： G06F13/1694 ,  G06F13/1657

摘要： In one embodiment of the invention, a replaceable memory apparatus is disclosed. The replaceable memory apparatus includes a first rectangular multilayer printed circuit board having a first side and a second side opposite the first side; a first male pluggable electrical connector mounted to the first side near a first edge; a first female pluggable electrical connector mounted to the second side; and first non-volatile memory mounted to the first side and the second side. The first female pluggable electrical connector is coupled to the first male pluggable electrical connector to feed through first signals. The first non-volatile memory is coupled to the first female pluggable electrical connector and the first male pluggable electrical connector to receive the first signals.

摘要翻译： 在本发明的一个实施例中，公开了一种可替换的存储装置。 可替换存储装置包括：第一矩形多层印刷电路板，具有第一侧和与第一侧相对的第二侧; 在第一边缘附近安装到第一侧的第一可插拔电连接器; 安装在第二侧的第一可插拔电插头; 以及安装到第一侧和第二侧的第一非易失性存储器。 第一可插拔电连接器可耦合到第一可插拔电连接器以馈送第一信号。 第一非易失性存储器耦合到第一可插拔电连接器和第一可插拔电连接器以接收第一信号。

公开(公告)号：US08555002B2

公开(公告)日：2013-10-08

申请号：US13443086

申请日：2012-04-10

申请人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

发明人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

IPC分类号： G06F13/00

CPC分类号： G06F12/1009 ,  G06F3/0604 ,  G06F3/0628 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0646 ,  G06F3/0647 ,  G06F3/068 ,  G06F3/0685 ,  G06F9/5016 ,  G06F12/0207 ,  G06F12/0223 ,  G06F12/0292 ,  G06F12/08 ,  G06F12/10 ,  G06F12/121 ,  G06F12/1475 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/205 ,  G06F2212/657 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/22

摘要： Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.

摘要翻译： 通过接收来自应用程序的命令来读取与映射到主存储器的虚拟地址相关联的数据来管理主存储器。 存储器控制器确定虚拟地址被映射到主存储器的对称存储器组件中的一个，并且访问指示如何与虚拟地址相关联的数据被访问的存储器使用特性。存储器控制器确定与 虚拟地址具有适合于主存储器的非对称存储器组件的访问特征，并将与虚拟地址相关联的数据加载到主存储器的非对称存储器组件。 在加载和使用存储器管理单元之后，从应用程序接收到用于读取与虚拟地址相关联的数据的命令，并且从非对称存储器组件检索与虚拟地址相关联的数据。

公开(公告)号：US08478931B1

公开(公告)日：2013-07-02

申请号：US13465790

申请日：2012-05-07

申请人： Vijay Karamcheti

发明人： Vijay Karamcheti

IPC分类号： G06F12/08

CPC分类号： G06F12/0246 ,  G06F12/06 ,  G06F12/109 ,  G06F17/30519 ,  G06F2212/205 ,  G06F2212/7201 ,  G11C16/102

摘要： A buffer pool for a database application is maintained in a volatile main memory component. A control portion that corresponds to a block of application data residing on a non-volatile, asymmetric memory component and that includes a reference to a location of the block of application data on the non-volatile, asymmetric memory component is added to the buffer pool maintained in the volatile main memory component. The control portion from the buffer pool maintained in the volatile main memory component that corresponds to the block of application data is accessed and the location of the block of application data on the non-volatile, asymmetric memory component is identified. Based on identifying the location of the block of application data on the non-volatile, asymmetric memory component, the database application is enabled to access the block of application data directly from the non-volatile, asymmetric memory component.

摘要翻译： 用于数据库应用程序的缓冲池被保存在易失性主存储器组件中。 对应于驻留在非易失性非对称存储器组件上并且包括对非易失性非对称存储器组件上的应用数据块的位置的引用的应用数据块的控制部分被添加到缓冲池 维持在易失性主存储器组件中。 访问保存在与应用数据块对应的易失性主存储器组件中的缓冲池的控制部分，并且识别非易失性非对称存储器组件上的应用数据块的位置。 基于识别非易失性非对称存储器组件上的应用数据块的位置，数据库应用程序能够直接从非易失性非对称存储器组件访问应用数据块。

公开(公告)号：US08417873B1

公开(公告)日：2013-04-09

申请号：US12490914

申请日：2009-06-24

申请人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy

发明人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy

IPC分类号： G06F13/00

CPC分类号： G06F12/0246 ,  G06F12/0866 ,  G06F13/1694 ,  G06F2212/211

摘要： In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.

摘要翻译： 在本发明的一个实施例中，公开了一种存储装置。 存储装置包括存储器阵列，块读/写控制器和随机存取读存储器控制器。 存储器阵列是块读/写可访问和随机读取可访问的。 块读/写控制器耦合在存储器阵列和外部互连之间。 块读/写控制器对存储器阵列执行块读/写操作，以访问其中的连续存储单元的块。 随机访问读存储器控制器与块读/写访问控制器并行地耦合在存储器阵列和外部互连之间。 随机存取读取存储器控制器对存储器阵列执行随机读取存储器操作以访问其中的随机存储器位置。

公开(公告)号：US08370548B2

公开(公告)日：2013-02-05

申请号：US12832921

申请日：2010-07-08

申请人： Vijay Karamcheti ,  Kumar Ganapathy ,  Kenneth Alan Okin ,  Rajesh Parekh

发明人： Vijay Karamcheti ,  Kumar Ganapathy ,  Kenneth Alan Okin ,  Rajesh Parekh

IPC分类号： G06F13/12

CPC分类号： G06F13/1657 ,  Y02D10/14

摘要： An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.

摘要翻译： 一种装置包括具有多个印刷电路板迹线的印刷电路板，安装在与多个印刷电路板迹线中的一个或多个印刷电路板迹线耦合的印刷电路板上的存储器控​​制器，多个非易失型存储器集成电路 耦合到印刷电路板，以及耦合在存储器控制器和多个非易失性类型的存储器集成电路之间的多个支持集成电路。

公开(公告)号：US20120198138A1

公开(公告)日：2012-08-02

申请号：US13441663

申请日：2012-04-06

申请人： Kenneth A. Okin ,  Vijay Karamcheti

发明人： Kenneth A. Okin ,  Vijay Karamcheti

IPC分类号： G06F12/00

CPC分类号： G06F12/02 ,  G06F11/1658 ,  G06F11/20 ,  G06F12/0246 ,  G06F12/06 ,  G06F12/08 ,  G06F12/10 ,  G06F2212/1032 ,  G06F2212/205 ,  G06F2212/7201 ,  G06F2212/7202 ,  G11C16/3418 ,  G11C16/3427

摘要： A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.

摘要翻译： 存储器控制器（MC）与重映射表相关联，以使得能够访问包括非对称存储器的存储器系统中的内容。 MC从系统的存储器管理单元（MMU）指定的物理地址从中央处理单元（CPU）接收对存储器读取或输入/输出（I / O）写入的请求。 通过将与CPU指令关联的虚拟地址转换为表示系统内存或I / O位置的物理地址，CPU使用MMU来管理CPU的存储器操作。 用于非对称存储器的MC被配置为处理MMU指定的物理地址作为附加类型的虚拟地址，在MMU指定的物理地址与该地址由MC关联的物理存储器地址之间创建一个抽象层 。 MC屏蔽CPU免受实现具有不对称组件的存储系统所需的计算复杂性。

公开(公告)号：US08205061B2

公开(公告)日：2012-06-19

申请号：US13048012

申请日：2011-03-15

申请人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

发明人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

IPC分类号： G06F13/00

CPC分类号： G06F12/1009 ,  G06F3/0604 ,  G06F3/0628 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0646 ,  G06F3/0647 ,  G06F3/068 ,  G06F3/0685 ,  G06F9/5016 ,  G06F12/0207 ,  G06F12/0223 ,  G06F12/0292 ,  G06F12/08 ,  G06F12/10 ,  G06F12/121 ,  G06F12/1475 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/205 ,  G06F2212/657 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/22

摘要： A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.

摘要翻译： 接收来自应用程序的命令以访问与映射到主存储器的一个或多个虚拟地址相关联的数据结构。 识别具有映射到对称存储器组件的组成地址的数据结构的虚拟地址的第一子集以及具有映射到非对称存储器组件的组成地址的数据结构的虚拟地址的第二子集。 访问与来自第一物理地址的虚拟地址相关联的数据和与来自第二物理地址的虚拟地址相关联的数据。 与对称和非对称存储器组件相关联的数据被应用程序访问，而不向应用程序提供在对称存储器组件或非对称存储器组件内是否访问数据的指示。

公开(公告)号：US08176233B1

公开(公告)日：2012-05-08

申请号：US12505386

申请日：2009-07-17

申请人： Vijay Karamcheti

发明人： Vijay Karamcheti

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F12/06 ,  G06F12/109 ,  G06F17/30519 ,  G06F2212/205 ,  G06F2212/7201 ,  G11C16/102

摘要： A buffer pool for a database application is maintained in a volatile main memory component. A control portion that corresponds to a block of application data residing on a non-volatile, asymmetric memory component and that includes a reference to a location of the block of application data on the non-volatile, asymmetric memory component is added to the buffer pool maintained in the volatile main memory component. The control portion from the buffer pool maintained in the volatile main memory component that corresponds to the block of application data is accessed and the location of the block of application data on the non-volatile, asymmetric memory component is identified. Based on identifying the location of the block of application data on the non-volatile, asymmetric memory component, the database application is enabled to access the block of application data directly from the non-volatile, asymmetric memory component.

摘要翻译： 用于数据库应用程序的缓冲池被保存在易失性主存储器组件中。 对应于驻留在非易失性非对称存储器组件上并且包括对非易失性非对称存储器组件上的应用数据块的位置的引用的应用数据块的控制部分被添加到缓冲池 维持在易失性主存储器组件中。 访问保存在与应用数据块对应的易失性主存储器组件中的缓冲池的控制部分，并且识别非易失性非对称存储器组件上的应用数据块的位置。 基于识别非易失性非对称存储器组件上的应用数据块的位置，数据库应用程序能够直接从非易失性非对称存储器组件访问应用数据块。