公开(公告)号：US07372384B1

公开(公告)日：2008-05-13

申请号：US11611408

申请日：2006-12-15

申请人： Bin Xu

发明人： Bin Xu

IPC分类号： H03M3/00

CPC分类号： H03M3/368 ,  H03M3/432 ,  H03M3/456 ,  H03M3/506

摘要： An ADC and method comprises a hybrid-type sigma-delta modulator comprising a digital delta-stage and an analog sigma-stage, wherein the analog sigma-stage comprises an analog low-pass filter adapted to only pass a low frequency audio band between 0-20 khz of a PWM wave, and wherein the digital delta-stage comprises a PWM wave generator; a pair of MOSFETs; and a power supply unit outputting voltage to the pair of MOSFETs. The ADC comprises a comparator attached to the hybrid-type sigma-delta modulator; a low-pass filter configured in a digital domain and for receiving a signal output of the comparator and remove high-frequency components of the comparator output above the audio band; a PWM back converter adapted to receive the filtered signal output and translate the digital low-pass filtered signal output to a power supply transient value in a digital format; and a dither signal source for injecting a dither signal to the digital delta-stage.

摘要翻译： 一种ADC和方法包括混合型Σ-Δ调制器，其包括数字增量级和模拟Σ级，其中模拟Σ级包括模拟低通滤波器，其适于仅通过低频音频带在0 -20khz的PWM波，并且其中所述数字增量级包括PWM波发生器; 一对MOSFET; 以及向所述一对MOSFET输出电压的电源单元。 ADC包括连接到混合型Σ-Δ调制器的比较器; 配置在数字域中的低通滤波器，用于接收比较器的信号输出，并去除音频带上方的比较器输出的高频分量; PWM逆转换器，其适于接收经滤波的信号输出，并将数字低通滤波信号输出转换为数字格式的电源瞬态值; 以及用于将抖动信号注入到数字三角形级的抖动信号源。

公开(公告)号：US07365378B2

公开(公告)日：2008-04-29

申请号：US11095373

申请日：2005-03-31

申请人： Elbert E. Huang ,  Philip J. Oldiges ,  Ghavam G. Shahidi ,  Christy S. Tyberg ,  Xinlin Wang ,  Robert L. Wisnieff

发明人： Elbert E. Huang ,  Philip J. Oldiges ,  Ghavam G. Shahidi ,  Christy S. Tyberg ,  Xinlin Wang ,  Robert L. Wisnieff

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L29/4991 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A MOSFET structure and method of fabricating the structure incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. The multi-layer sidewall spacer is formed with a gap layer having a dielectric constant equal to one and a permeable low-K (e.g., less than 3.5) dielectric layer. Alternatively, the multi-layer sidewall spacer is formed with a first L-shaped dielectric layer having a permittivity value of less than approximately three and a second dielectric layer. The multi-layer spacer may also have a third nitride or oxide spacer layer. This third spacer layer provides increased structural integrity.

摘要翻译： MOSFET结构和制造该结构的方法包括多层侧壁间隔物，以抑制栅极导体和源/漏扩展之间的寄生重叠电容，而不降低驱动电流，从而影响整体MOSFET性能。 多层侧壁间隔物形成有介电常数等于1的间隙层和可渗透的低K（例如，小于3.5）的电介质层。 或者，多层侧壁间隔物形成有介电常数值小于约三的第一L形介电层和第二电介质层。 多层间隔物也可以具有第三氮化物或氧化物隔离层。 该第三间隔层提供增加的结构完整性。

公开(公告)号：US07362698B2

公开(公告)日：2008-04-22

申请号：US10707900

申请日：2004-01-22

申请人： James Edward Christensen ,  Edith Helen Stern ,  Arup Acharya ,  Zon-Yin Shae ,  Rose Marie Williams

发明人： James Edward Christensen ,  Edith Helen Stern ,  Arup Acharya ,  Zon-Yin Shae ,  Rose Marie Williams

IPC分类号： H04L12/26

CPC分类号： H04L29/06027 ,  H04L29/12122 ,  H04L29/1216 ,  H04L61/1547 ,  H04L61/157 ,  H04L65/1069 ,  H04L67/2814 ,  H04M3/42 ,  H04M3/42059 ,  H04M3/42229 ,  H04M3/436 ,  H04M2203/2072

摘要： A method for routing a communication connection request includes the steps of obtaining context information from a communication connection requestor in response to a communication connection request. The steps further include using the context information to determine a communication connection action, and connecting the communication connection requestor based upon the connection action.

摘要翻译： 用于路由通信连接请求的方法包括以下步骤：响应于通信连接请求从通信连接请求者获取上下文信息。 所述步骤还包括使用所述上下文信息来确定通信连接动作，以及基于所述连接动作来连接所述通信连接请求者。

公开(公告)号：US07361584B2

公开(公告)日：2008-04-22

申请号：US10904329

申请日：2004-11-04

申请人： Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Stephen K. Loh ,  Ping-Chuan Wang

发明人： Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Stephen K. Loh ,  Ping-Chuan Wang

IPC分类号： H01L21/4763

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/7688 ,  H01L22/24 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the substrate; a marker layer over the dielectric layer; a liner over the marker layer and dielectric layer; and a metal layer over the liner, wherein the marker layer comprises ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of the metal layer and the liner over the marker layer. Moreover, the marker layer comprises a separate layer from the dielectric layer. Additionally, the ultraviolet detectable material comprises fluorescent material or phosphorescent material.

摘要翻译： 用于在镶嵌工艺中抛光之后检测残留衬垫材料的方法和结构包括：包括衬底的集成电路; 介电层; 电介质层上的标记层; 标记层和电介质层上的衬垫; 以及在所述衬里上的金属层，其中所述标记层包括紫外线可检测材料，其在通过紫外线激发时表示在所述标记层上不存在所述金属层和所述衬垫。 此外，标记层包括与电介质层分离的层。 另外，紫外线可检测材料包括荧光材料或磷光材料。

公开(公告)号：US07356599B2

公开(公告)日：2008-04-08

申请号：US10064943

申请日：2002-08-30

申请人： Bastian Pochon ,  Paolo Scotton

发明人： Bastian Pochon ,  Paolo Scotton

IPC分类号： G06F15/16

CPC分类号： H04L43/00 ,  H04L41/12 ,  H04L43/10 ,  H04L63/0227 ,  H04L63/1408

摘要： A method that allows the normalization of traffic data that is simultaneously transferred to a network intrusion detection system (NIDS) and monitored end-systems located in a network, such as a TCP/IP network, in which packets of data such as IP datagrams, are fragmented and reassembled. Accordingly, the information of received fragments and/or the topology of the network comprising the network intrusion detection system (NIDS) and the monitored end-systems are entered into a normalization table, that is dynamically established and maintained. Subsequently packets of data such as IP datagrams are modified, redirected or discarded in case that ambiguities are detected when comparing information contained in the normalization table with information contained in the headers of the received data packets.

摘要翻译： 允许同时传送到位于诸如TCP / IP网络的网络中的网络入侵检测系统（NIDS）和被监视的终端系统的业务数据的归一化方法，其中诸如IP数据报， 被分散和重组。 因此，包括网络入侵检测系统（NIDS）和所监视的终端系统的接收到的片段和/或网络拓扑的信息被输入到动态建立和维护的规范化表中。 随后，当将归一化表中包含的信息与包含在接收到的数据分组的报头中的信息进行比较时，检测到模糊度的情况下，数据包（例如IP数据报）被修改，重定向或丢弃。

公开(公告)号：US07353477B2

公开(公告)日：2008-04-01

申请号：US10709327

申请日：2004-04-28

申请人： David J. Hathaway ,  Kerim Kalafala

发明人： David J. Hathaway ,  Kerim Kalafala

IPC分类号： G06F17/50

CPC分类号： H04L41/14 ,  H04L43/0852 ,  H04L43/16

摘要： A method of performing node-based static timing analysis on a digital network and a program storage device for implementing the method, wherein the method comprises partitioning timing delays in the digital network into portions attributable to a factor of interest and portions attributable to other factors; multiplying the timing delays by different weights based on the factor of interest to produce weighted timing delays; and using the multiplied timing delays to determine a relative impact of the factor of interest on the various paths in the digital network. The method further comprises setting arrival times of timing signals at digital network path start points to zero and identifying digital network paths whose timing delays are dominated by a particular factor of interest. The different weights comprise any of a positive weight, a negative weight, and a zero weight.

摘要翻译： 一种在数字网络上执行基于节点的静态时序分析的方法和用于实现该方法的程序存储设备，其中该方法包括将数字网络中的定时延迟分成可归因于其他因素的关注因素和部分; 基于感兴趣的因素将定时延迟乘以不同的权重以产生加权定时延迟; 并且使用相乘的定时延迟来确定感兴趣因素对数字网络中各种路径的相对影响。 该方法还包括将数字网络路径起点处的定时信号的到达时间设置为零，并且识别其定时延迟由特定感兴趣的因素支配的数字网络路径。 不同的重量包括正重量，负重量和零重量中的任何一种。

公开(公告)号：US07350160B2

公开(公告)日：2008-03-25

申请号：US10604059

申请日：2003-06-24

申请人： Charles N. Perez ,  Steven H. Voldman

发明人： Charles N. Perez ,  Steven H. Voldman

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： The invention displays a guard ring within an integrated circuit design by determining positions of the logic devices within the integrated circuit design, incorporating the guard ring into the integrated circuit design, and displaying the logic devices and the guard ring either graphically, semantically, or symbolically in a single display. The symbolic display comprises a parameterized symbol. The parameterized symbol displays parameters including the type of circuit, the type of guard ring and the efficiency of the guard ring. The invention displays the logic devices and the guard ring graphically by illustrating relative positions of the logic devices and the guard ring.

摘要翻译： 本发明通过确定集成电路设计内的逻辑器件的位置，将集成电路设计中的保护环结合到集成电路设计中来显示保护环，并以图形，语义或符号方式显示逻辑器件和保护环 在一个单一的显示。 符号显示包括参数化符号。 参数化符号显示包括电路类型，保护环类型和保护环效率的参数。 本发明通过示出逻辑设备和保护环的相对位置以图形方式显示逻辑设备和保护环。

公开(公告)号：US07349751B2

公开(公告)日：2008-03-25

申请号：US11538821

申请日：2006-10-05

申请人： Brian T. Denton ,  Kenneth J. Fordyce

发明人： Brian T. Denton ,  Kenneth J. Fordyce

IPC分类号： G06F19/00

CPC分类号： G05B19/41865 ,  G05B2219/31411 ,  G05B2219/32247 ,  G05B2219/32267 ,  G05B2219/32271 ,  G05B2219/32293 ,  G05B2219/45028 ,  Y02P90/20

摘要： Disclosed is a method of controlling a manufacturing system. The invention automatically monitors current levels of partially completed products waiting to be processed by a tool (or group of tools) and determines whether the current levels exceed a predetermined limit. If the current levels do exceed the predetermined limit, the invention performs an optimization process. However, if the current levels do not exceed the predetermined limit, the invention performs a dispatching process. In this dispatching process, the invention automatically projects future levels of partially completed products that will be supplied to the tool to identify a future work-in-process (WIP) bubble. The WIP bubble occurs when larger than normal amounts of partially completed products are supplied to the tool. The invention automatically adjusts the operating parameters of the tool based upon both the current levels and the future levels.

摘要翻译： 公开了一种控制制造系统的方法。 本发明自动监视等待由工具（或一组工具）处理的部分完成的产品的当前水平，并确定当前水平是否超过预定极限。 如果当前水平超过预定极限，本发明进行优化处理。 然而，如果当前电平不超过预定限度，则本发明执行调度处理。 在这个调度过程中，本发明会自动将未来的部分完成产品的水平提供给工具，以识别未来的在制品（WIP）泡沫。 当大于正常量的部分完成的产品被提供给工具时，会出现WIP气泡。 本发明基于当前水平和未来水平自动调整工具的操作参数。

公开(公告)号：US07339364B2

公开(公告)日：2008-03-04

申请号：US11424881

申请日：2006-06-19

申请人： Brandon R. Kam ,  Stephen D. Wyatt

发明人： Brandon R. Kam ,  Stephen D. Wyatt

IPC分类号： G01R23/175 ,  H03L7/06

CPC分类号： G01R31/31709 ,  G01R29/26 ,  H03L7/07 ,  H03L7/0814

摘要： An improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal, the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.

摘要翻译： 改进的内置自测（BIST）电路和相关方法用于测量时钟信号的相位和/或周期与周期的抖动，BIST电路实现可变游标数字延迟锁定线方法。 具体地，BIST电路的实施例包括数字延迟锁定环和游标延迟线，分别用于电路的粗调和微调部分。 此外，BIST电路是可变的，因为电路的分辨率由芯片变为芯片，而数字是由标准数字逻辑元件实现的。

公开(公告)号：US07334032B2

公开(公告)日：2008-02-19

申请号：US10309606

申请日：2002-12-04

申请人： David D. Chambliss ,  Divyesh Jadav

发明人： David D. Chambliss ,  Divyesh Jadav

IPC分类号： G06F15/173 ,  G06F15/00

CPC分类号： G06F3/0659 ,  G06F3/0617 ,  G06F3/0653 ,  G06F3/067 ,  G06F11/3414 ,  G06F2206/1012

摘要： A method and structure for a multi-workload storage system is disclosed that is adapted to determine if an additional workload can be placed on the storage system. The invention has storage elements and a proxy load generator connected to the storage elements. The proxy load generator is adapted to create a proxy workload based on an additional workload from a potential client. The proxy workload has a reduced duty cycle when compared to a duty cycle of said additional workload. A control server is connected to the storage elements and the proxy load generator. The control server applies the proxy workload to the storage elements during discontinuous time slices.

摘要翻译： 公开了一种用于多工作负载存储系统的方法和结构，其适于确定是否可以在存储系统上放置额外的工作负载。 本发明具有连接到存储元件的存储元件和代理负载发生器。 代理负载生成器适于基于潜在客户端的额外工作负载创建代理工作负载。 与所述额外工作负载的占空比相比，代理工作负载具有减少的占空比。 控制服务器连接到存储元件和代理负载生成器。 控制服务器在不连续时间片段期间将代理工作负载应用于存储元件。