公开(公告)号：US06660607B2

公开(公告)日：2003-12-09

申请号：US09822587

申请日：2001-03-30

Applicant: Basanth Jagannathan

Inventor： Basanth Jagannathan

IPC: H01L21331

CPC classification number: H01L29/66242

Abstract: A method for fabricating a heterojunction bipolar transistor having collector, base and emitter regions is disclosed. In an exemplary embodiment of the invention, the method includes forming a silicon epitaxial layer upon a substrate, the silicon epitaxial layer defining the collector region. An oxide stack is formed upon the silicon epitaxial layer and a nitride layer is then formed upon the oxide stack. Next, an emitter opening is defined within the nitride layer before a base cavity is formed within the oxide stack. The base cavity extends laterally beyond the width of the emitter opening. A silicon-germanium epitaxial layer is grown within the base cavity, the silicon-germanium epitaxial layer defining the base region. Finally, a polysilicon layer is deposited upon said silicon-germanium epitaxial layer, the polysilicon layer defining the emitter region.

公开(公告)号：US06506656B2

公开(公告)日：2003-01-14

申请号：US09811859

申请日：2001-03-19

Applicant: Gregory G. Freeman ,  Basanth Jagannathan ,  Shwu-Jen Jeng ,  Jeffrey B. Johnson

Inventor： Gregory G. Freeman ,  Basanth Jagannathan ,  Shwu-Jen Jeng ,  Jeffrey B. Johnson

IPC: H01L21331

CPC classification number: H01L29/66287 ,  H01L29/0821 ,  H01L29/36 ,  H01L29/66242

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance with a stepped collector dopant profile that reduces emitter-collector transit time and parasitic resistance with minimal increase in parasitic capacitances. The preferred stepped collector dopant profile includes a shallow implant and a deeper implant. The shallow implant reduces the base-collector space-charge region width, reduce resistance, and tailors the collector-base breakdown characteristics. The deeper implant links the buried collector to the subcollector and provides a low resistance path to the subcollector. The stepped collector dopant profile has minimal impact on the collector-base capacitance outside the intrinsic region of the device since the higher dopant is compensated by, or buried in, the extrinsic base dopants outside the intrinsic region.

公开(公告)号：US08187930B2

公开(公告)日：2012-05-29

申请号：US11923686

申请日：2007-10-25

Applicant: Basanth Jagannathan ,  John J. Pekarik ,  Christopher M. Schnabel

Inventor： Basanth Jagannathan ,  John J. Pekarik ,  Christopher M. Schnabel

IPC: H01L21/337

CPC classification number: H01L29/78 ,  H01L23/4824 ,  H01L29/1087

Abstract: Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.

Abstract translation: 制造半导体器件的方法包括在衬底中形成源极和漏极，在源极和漏极之间的衬底上形成栅极，形成与源电接触的衬底接触，以及形成与源极的电接触， 漏极和栅极以及基板。

公开(公告)号：US07713829B2

公开(公告)日：2010-05-11

申请号：US11562735

申请日：2006-11-22

Applicant: Jack Oon Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

Inventor： Jack Oon Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

IPC: H01L21/8222 ,  H01L29/737

CPC classification number: H01L29/66242 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

Abstract translation: 提供了在发射极和集电极区域之间基本上不存在位错缺陷的SiGe双极晶体管及其形成方法。 SiGe双极晶体管包括第一导电类型的集电极区域; 形成在所述集电区域的一部分上的SiGe基区; 以及形成在所述基极区域的一部分上的所述第一导电类型的发射极区域，其中所述集电极区域和所述基极区域在其中连续地包括碳。 SiGe基区进一步掺硼。

公开(公告)号：US06881259B1

公开(公告)日：2005-04-19

申请号：US09633857

申请日：2000-08-07

Applicant: David C. Ahlgren ,  Jack Oon Chu ,  Basanth Jagannathan ,  Ryan W. Wuthrich

Inventor： David C. Ahlgren ,  Jack Oon Chu ,  Basanth Jagannathan ,  Ryan W. Wuthrich

IPC: C30B25/16 ,  C30B29/52

CPC classification number: C30B29/52 ,  C30B25/165

Abstract: Analysis of residual gases from a process for depositing a film containing silicon on a crystalline silicon surface to determine partial pressure of hydrogen evolved during deposition develops a signature which indicates temperature and/or concentration of germanium at the deposition surface. Calibration and collection of hydrogen partial pressure data at a rate which is high relative to film deposition rate allows real-time, in-situ, non-destructive determination of material concentration profile over the thickness of the film and/or monitoring the temperature of a silicon film deposition process with increased accuracy and resolution to provide films of a desired thickness with high accuracy.

Abstract translation: 分析来自用于在晶体硅表面上沉积含硅的膜的工艺的残余气体，以确定在沉积期间释放出来的氢的分压，形成指示沉积表面的锗的温度和/或浓度的标记。 以相对于膜沉积速率高的速率校准和收集氢分压数据允许在膜的厚度上的材料浓度分布的实时，原位，非破坏性测定和/或监测膜的温度 硅膜沉积工艺具有更高的精度和分辨率，以高精度提供所需厚度的膜。

公开(公告)号：US06875279B2

公开(公告)日：2005-04-05

申请号：US09683088

申请日：2001-11-16

Applicant: Jack O. Chu ,  Basanth Jagannathan ,  Ryan Wayne Wuthrich

Inventor： Jack O. Chu ,  Basanth Jagannathan ,  Ryan Wayne Wuthrich

IPC: C23C16/44 ,  C23C16/54 ,  C30B25/08 ,  C30B25/14 ,  C23C16/00

CPC classification number: C23C16/54 ,  C23C16/4412 ,  C30B25/08 ,  C30B25/14 ,  Y10T117/10

Abstract: An apparatus and method for forming at least a portion of an electronic device include a High Vacuum-Chemical Vapor Deposition (UHV-CVD) system and a Low Pressure-Chemical Vapor Deposition (LPCVD) system using a common reactor. The invention overcomes the problem of silicon containing wafers being dipped in HF acid prior to CVD processing, and the problem of surface passivation between processes in multiple CVD reactors.

Abstract translation: 用于形成电子器件的至少一部分的装置和方法包括使用公共反应器的高真空 - 化学气相沉积（UHV-CVD）系统和低压 - 化学气相沉积（LPCVD）系统。 本发明克服了在CVD处理之前将含硅晶片浸入HF酸中的问题，以及在多个CVD反应器中的工艺之间的表面钝化的问题。

公开(公告)号：US06787427B2

公开(公告)日：2004-09-07

申请号：US10676171

申请日：2003-10-01

Applicant: David R. Greenberg ,  Basanth Jagannathan ,  Shwu-Jen Jeng ,  Joseph T. Kocis ,  Samuel C. Ramac ,  David M. Rockwell

Inventor： David R. Greenberg ,  Basanth Jagannathan ,  Shwu-Jen Jeng ,  Joseph T. Kocis ,  Samuel C. Ramac ,  David M. Rockwell

IPC: H01L21331

CPC classification number: H01L29/66242 ,  H01L29/7378

Abstract: A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-situ P-doped emitter layer atop a patterned SiGe base structure. The in-situ P-doped emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon. The SiGe HBT structure including the above mentioned bilayer emitter is also described herein.

Abstract translation: 提供一种制造SiGe异质结双极晶体管（HBT）的方法，其导致具有可控电流增益和改善的击穿电压的SiGe HBT。 具有这些特性的SiGe HBT通过在图案化的SiGe基底结构顶上形成原位P掺杂的发射极层来制造。 原位P掺杂发射极层是原位P掺杂的a：Si和原位P掺杂多晶硅的双层。 包括上述双层发射体的SiGe HBT结构也在此描述。

公开(公告)号：US06744079B2

公开(公告)日：2004-06-01

申请号：US09683983

申请日：2002-03-08

Applicant: Basanth Jagannathan ,  Alvin J. Joseph ,  Xuefeng Liu ,  Kathryn T. Schonenberg ,  Ryan W. Wuthrich

Inventor： Basanth Jagannathan ,  Alvin J. Joseph ,  Xuefeng Liu ,  Kathryn T. Schonenberg ,  Ryan W. Wuthrich

IPC: H01L31072

CPC classification number: H01L29/66242 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

Abstract: A high performance SiGe HBT that has a SiGe layer with a peak Ge concentration of at least approximately 20% and a boron-doped base region formed therein having a thickness. The base region includes diffusion-limiting impurities substantially throughout its thickness, at a peak concentration below that of boron in the base region. Both the base region and the diffusion-limiting impurities are positioned relative to a peak concentration of Ge in the SiGe layer so as to optimize both performance and yield.

Abstract translation: 具有峰值Ge浓度至少为20％的SiGe层和其中形成有硼掺杂基底区域的高性能SiGe HBT具有厚度。 碱性区域在其整个厚度上基本上包括扩散限制性杂质，峰值浓度低于碱性区域中硼的峰值浓度。 碱性区域和扩散限制杂质都相对于SiGe层中的Ge的峰值浓度定位，以便优化性能和产率。

公开(公告)号：US06656809B2

公开(公告)日：2003-12-02

申请号：US10047975

申请日：2002-01-15

Applicant: David R. Greenberg ,  Basanth Jagannathan ,  Shwu-Jen Jeng ,  Joseph T. Kocis ,  Samuel C. Ramac ,  David M. Rockwell

Inventor： David R. Greenberg ,  Basanth Jagannathan ,  Shwu-Jen Jeng ,  Joseph T. Kocis ,  Samuel C. Ramac ,  David M. Rockwell

IPC: G01R3126

CPC classification number: H01L29/66242 ,  H01L29/7378

Abstract: A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-situ P-doped emitter layer atop a patterned SiGe base structure. The in-situ P-doped emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon. The SiGe HBT structure including the above mentioned bilayer emitter is also described herein.

Abstract translation: 提供一种制造SiGe异质结双极晶体管（HBT）的方法，其导致具有可控电流增益和改善的击穿电压的SiGe HBT。 具有这些特性的SiGe HBT通过在图案化的SiGe基底结构顶上形成原位P掺杂的发射极层来制造。 原位P掺杂发射极层是原位P掺杂的a：Si和原位P掺杂多晶硅的双层。 包括上述双层发射体的SiGe HBT结构也在此描述。

公开(公告)号：US06426265B1

公开(公告)日：2002-07-30

申请号：US09774126

申请日：2001-01-30

Applicant: Jack Oon Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

Inventor： Jack Oon Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

IPC: H01L21331

CPC classification number: H01L29/66242 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.