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    Organic light emitting device and method of manufacturing the same
    21.
    发明申请
    Organic light emitting device and method of manufacturing the same 审中-公开
    有机发光装置及其制造方法

    公开(公告)号：US20110248259A1

    公开(公告)日：2011-10-13

    申请号：US13064670

    申请日：2011-04-07

    Applicant: Il-Soo Oh ,  Chang-Ho Lee ,  Hee-Joo Ko ,  Se-Jin Cho ,  Hyung-Jun Song ,  Jin Young Yun ,  Jong-Hyuk Lee

    Inventor： Il-Soo Oh ,  Chang-Ho Lee ,  Hee-Joo Ko ,  Se-Jin Cho ,  Hyung-Jun Song ,  Jin Young Yun ,  Jong-Hyuk Lee

    IPC: H01L51/50 ,  H01L51/40

    CPC classification number: H01L51/5231 ,  H01L27/3248 ,  H01L51/5088

    Abstract: An organic light emitting device and a method of manufacturing the same, the device including a substrate; a thin film transistor on the substrate, the thin film transistor including source and drain electrodes, an oxide semiconductor layer, a gate electrode, and a gate insulating layer that insulates the gate electrode from the source and drain electrodes; a first insulating layer on the thin film transistor; a cathode on the first insulating layer, the cathode being connected to one of the source and drain electrodes of the thin film transistor; a first layer on the cathode, the first layer including a first material, the first material including at least one of metal, metal sulfide, metal oxide, and metal nitride; an organic layer on the first layer; and an anode on the organic layer.

    Abstract translation: 一种有机发光器件及其制造方法，所述器件包括衬底; 薄膜晶体管，薄膜晶体管，其包括源电极和漏电极，氧化物半导体层，栅电极和栅极绝缘层，其使栅电极与源电极和漏电极绝缘; 薄膜晶体管上的第一绝缘层; 在所述第一绝缘层上的阴极，所述阴极连接到所述薄膜晶体管的源极和漏极之一; 阴极上的第一层，所述第一层包括第一材料，所述第一材料包括金属，金属硫化物，金属氧化物和金属氮化物中的至少一种; 第一层上的有机层; 和有机层上的阳极。

    ETCHANT COMPOSITION FOR METAL WIRING AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL USING THE SAME
    24.
    发明申请
    ETCHANT COMPOSITION FOR METAL WIRING AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL USING THE SAME 审中-公开
    用于金属接线的蚀刻组合物及其制造薄膜晶体管阵列板的方法

    公开(公告)号：US20110177680A1

    公开(公告)日：2011-07-21

    申请号：US12902018

    申请日：2010-10-11

    Applicant: Byeong-Jin LEE ,  Hong Sik PARK ,  Tai-Hyung RHEE ,  Yong-Sung SONG ,  Choung-Woo PARK ,  Chang-Ho LEE

    Inventor： Byeong-Jin LEE ,  Hong Sik PARK ,  Tai-Hyung RHEE ,  Yong-Sung SONG ,  Choung-Woo PARK ,  Chang-Ho LEE

    IPC: H01L21/20 ,  C09K13/00 ,  C09K13/08

    CPC classification number: H01L21/32134 ,  C09K13/08 ,  C23F1/18 ,  C23F1/26 ,  C23F1/44

    Abstract: The present invention relates to an etchant for wet etching a wiring that includes copper, where the etchant includes approximately 5 to approximately 25 wt % of a peroxide, approximately 0.5 to approximately 5 wt % of an oxidant, approximately 0.1 to approximately 1 wt % of a fluoride-based compound and approximately 1 to approximately 10 wt % of a glycol. The etchant can provide an etching rate that is suitable to many processes, and produces an appropriate etching amount as well as an appropriate taper angle.In addition, the etchant exhibits advantages including relatively low viscosity as compared to phosphoric acid-based etchants, relatively uniform etching characteristics, and relative stability as compared to peroxide-based etchants.

    Abstract translation: 本发明涉及用于湿蚀刻包括铜的布线的蚀刻剂，其中蚀刻剂包括约5至约25重量％的过氧化物，约0.5至约5重量％的氧化剂，约0.1至约1重量％的氧化剂， 氟化物基化合物和约1至约10重量％的二醇。 蚀刻剂可以提供适合于许多工艺的蚀刻速率，并且产生适当的蚀刻量以及适当的锥角。 此外，与基于磷酸的蚀刻剂相比，蚀刻剂具有相对低的粘度，相对均匀的蚀刻特性以及与基于过氧化物的蚀刻剂相比的相对稳定性的优点。

    Multipath accessible semiconductor memory device with host interface between processors
    25.
    发明授权
    Multipath accessible semiconductor memory device with host interface between processors 有权
    多路径可访问的半导体存储器件，具有处理器之间的主机接口

    公开(公告)号：US07941612B2

    公开(公告)日：2011-05-10

    申请号：US11829859

    申请日：2007-07-27

    Applicant: Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Dong-Hyuk Lee ,  Jong-Wook Park ,  Ho-Cheol Lee ,  Mi-Jo Kim ,  Jung-Sik Kim ,  Chang-Ho Lee

    Inventor： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Dong-Hyuk Lee ,  Jong-Wook Park ,  Ho-Cheol Lee ,  Mi-Jo Kim ,  Jung-Sik Kim ,  Chang-Ho Lee

    IPC: G06F12/00

    CPC classification number: G11C7/1075 ,  G11C7/1012 ,  G11C11/4096

    Abstract: A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.

    Abstract translation: 多路可及半导体存储器件提供处理器之间的接口功能。 存储器设备可以包括具有可操作地耦合到两个或更多个端口的共享存储器区域的存储单元阵列，该两个或多个端口可由两个或多个处理器独立地访问;访问路径形成单元，用于在一个端口和共享之间形成数据访问路径 响应于由处理器施加的外部信号的存储区域以及具有信号量区域和由两个或多个处理器在共享存储器区域中可访问的邮箱区域的接口单元，以提供用于两个或多个处理器之间的通信的接口功能。

    Limited current circuit of digital inverter for LCD backlight
    26.
    发明授权
    Limited current circuit of digital inverter for LCD backlight 有权
    LCD背光数字逆变器有限电流电路

    公开(公告)号：US07911147B2

    公开(公告)日：2011-03-22

    申请号：US11646720

    申请日：2006-12-27

    Applicant: Oh-Sang Kwon ,  Chang-Ho Lee ,  Yong-Kon Lee

    Inventor： Oh-Sang Kwon ,  Chang-Ho Lee ,  Yong-Kon Lee

    IPC: H05B37/00

    CPC classification number: H05B41/2858 ,  Y02B20/186

    Abstract: A limited current circuit of this invention comprising: a transformer that raises an alternating current (AC) power supplied from the digital inverter to an AC voltage of a high voltage to light a lamp; a voltage/current detection unit that detects at least one of the current and voltage supplied to the lamp; an A/D converter that converts the detected voltage/current value of analog to a digital value; and a microcontroller unit (MCU) that induces an LCC check point after the start of a striking process, compares at least one of the output current value and voltage value from the transformer with a preset reference value on the basis of an output signal of the A/D converter and then shuts down the inverter when the output current value or voltage value is determined to be abnormal, wherein the reference value comprises at least one of the current value and voltage value measured at the LCC check point when an object having noninductive resistance is not contacted to the inverter.

    Abstract translation: 本发明的有限电流电路包括：变压器，其将从数字逆变器提供的交流电（AC）电力提高到高电压的AC电压以点亮灯; 电压/电流检测单元，其检测提供给所述灯的电流和电压中的至少一个; A / D转换器，其将检测到的模拟电压/电流值转换为数字值; 以及在触发过程开始之后引起LCC检查点的微控制器单元（MCU），将来自变压器的输出电流值和电压值中的至少一个与预设的参考值进行比较，基于输出信号 A / D转换器，然后当输出电流值或电压值被确定为异常时，关闭逆变器，其中参考值包括当具有非导体的物体时在LCC检查点测量的电流值和电压值中的至少一个 电阻不接触逆变器。

    Systems, methods, and apparatuses for complementary metal oxide semiconductor (CMOS) antenna switches using body switching in multistacking structure
    27.
    发明授权
    Systems, methods, and apparatuses for complementary metal oxide semiconductor (CMOS) antenna switches using body switching in multistacking structure 有权
    在多层结构中使用身体切换的互补金属氧化物半导体（CMOS）天线开关的系统，方法和装置

    公开(公告)号：US07890063B2

    公开(公告)日：2011-02-15

    申请号：US11857322

    申请日：2007-09-18

    Applicant: Minsik Ahn ,  Chang-Ho Lee ,  Changhyuk Cho ,  Jaejoon Chang ,  Wangmyong Woo ,  Haksun Kim ,  Joy Laskar

    Inventor： Minsik Ahn ,  Chang-Ho Lee ,  Changhyuk Cho ,  Jaejoon Chang ,  Wangmyong Woo ,  Haksun Kim ,  Joy Laskar

    IPC: H04B1/44

    CPC classification number: H03K17/693 ,  H03K17/063 ,  H03K17/102 ,  H03K2217/0018 ,  H04B1/48

    Abstract: Embodiments of the invention may provide for a CMOS antenna switch, which may be referred to as a CMOS SP4T switch. The CMOS antenna switch may operate at a plurality of frequencies, perhaps around 900 MHz and 1.9 GHz according to an embodiment of the invention. The CMOS antenna switch may include both a receiver switch and a transmit switch. The receiver switch may utilize a multi-stack transistor with body substrate tuning to block high power signals from the transmit path as well as to maintain low insertion loss at the receiver path. On the other hand, in the transmit switch, a body substrate tuning technique may be applied to maintain high power delivery to the antenna. Example embodiments of the CMOS antenna switch may provide for 31 dBm P 1 dB at both bands (e.g., 900 MHz and 1.8 GHz). In addition, a 0.9 dB and −1.1 dB insertion loss at 900 MHz and 1.9 GHz, respectively, may be obtained according to example embodiments of the invention.

    Abstract translation: 本发明的实施例可以提供CMOS天线开关，其可以被称为CMOS SP4T开关。 根据本发明的实施例，CMOS天线开关可以以多个频率操作，可能大约在900MHz和1.9GHz。 CMOS天线开关可以包括接收器开关和发送开关。 接收器开关可以利用具有主体衬底调谐的多层晶体管来阻挡来自发射路径的高功率信号以及在接收器路径处保持低的插入损耗。 另一方面，在发送开关中，可以应用主体衬底调谐技术来保持对天线的高功率输送。 CMOS天线开关的示例实施例可以在两个频带（例如，900MHz和1.8GHz）处提供31dBm的P 1 dB。 此外，根据本发明的示例实施例，可以分别获得在900MHz和1.9GHz处的0.9dB和-1.1dB的插入损耗。

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