公开(公告)号：US20080113641A1

公开(公告)日：2008-05-15

申请号：US11734435

申请日：2007-04-12

申请人： Chan-young Jeong ,  Chang-sik Yoo ,  Jin-soo Park ,  Heung-bae Lee ,  Young-eil Kim

发明人： Chan-young Jeong ,  Chang-sik Yoo ,  Jin-soo Park ,  Heung-bae Lee ,  Young-eil Kim

IPC分类号： H04B1/26 ,  H04B15/00

CPC分类号： H04B1/0082

摘要： A radio communication apparatus and a frequency generating method thereof the communication apparatus including a frequency generator to generate a plurality of local oscillator (LO) frequencies; and a mixer to convert a frequency of an input signal by mixing the input signal with at least two of the LO frequencies generated by the frequency generator. As the LO frequencies are generated using the single VCO to support the radio communication standard of the multiple bands, the circuit area can be reduced and the multimode and multiband can be supported with one chip.

摘要翻译： 一种无线电通信装置及其频率产生方法，该通信装置包括频率发生器以产生多个本地振荡器（LO）频率; 以及混频器，用于通过将输入信号与由频率发生器产生的至少两个LO频率进行混合来转换输入信号的频率。 由于使用单个VCO产生LO频率以支持多个频带的无线电通信标准，所以可以减少电路面积，并且可以通过一个芯片来支持多模和多频带。

公开(公告)号：US20080101524A1

公开(公告)日：2008-05-01

申请号：US11819807

申请日：2007-06-29

申请人： Chun-Seok Jeong ,  Jae-Jin Lee ,  Chang-Sik Yoo ,  Jung-June Park ,  Young-Suk Seo

发明人： Chun-Seok Jeong ,  Jae-Jin Lee ,  Chang-Sik Yoo ,  Jung-June Park ,  Young-Suk Seo

IPC分类号： H03D3/24

CPC分类号： H03D13/004

摘要： A clock data recovery apparatus includes a phase looked loop unit, a voltage control delay line, a phase detection unit, a charge pump unit, and a loop filter unit. The phase looked loop unit outputs a plurality of clock signals which are different from each other in phase and of which frequency is lower than that of data. The voltage control delay line outputs recovered clock signals by delaying the clock signals according to input voltage levels. The phase detection unit outputs recovered data in synchronization with the clock signals, respectively and outputs increment and decrement signals which have wider pulse width than the data by comparing the recovered clock signals with the data. The charge pump unit outputs a corresponding current in response to the increment and decrement signals. The loop filter unit determines an amount of delay in the voltage control delay line by outputting the voltage.

摘要翻译： 时钟数据恢复装置包括相位循环单元，电压控制延迟线，相位检测单元，电荷泵单元和环路滤波器单元。 相位循环单元输出相位不同的多个时钟信号，其频率低于数据的时钟信号。 电压控制延迟线通过根据输入电压电平延迟时钟信号来输出恢复的时钟信号。 相位检测单元分别与时钟信号同步地输出恢复的数据，并通过将恢复的时钟信号与数据进行比较，输出比数据宽的脉冲宽度的增减信号。 电荷泵单元响应于增量和减量信号输出相应的电流。 环路滤波器单元通过输出电压来确定电压控制延迟线中的延迟量。

公开(公告)号：US07313715B2

公开(公告)日：2007-12-25

申请号：US10043047

申请日：2002-01-09

申请人： Chang-sik Yoo ,  Byung-se So ,  Kye-hyun Kyung

发明人： Chang-sik Yoo ,  Byung-se So ,  Kye-hyun Kyung

IPC分类号： G06F1/04

CPC分类号： G11C7/1072 ,  G11C7/10

摘要： A memory system having a stub-bus configuration transmits a free-running clock through the same path as data signals. A single clock domain is employed for both read and write operations. For both operations, the read or write clock signal is routed through the same transmission path as the data, thereby increasing system transfer rates by maximizing the window of data validity. In this manner, data bus utilization is increased due to the elimination of a need for a preamble interval for the strobe signal, and pin count on the memory module connectors is therefore reduced.

摘要翻译： 具有短路总线配置的存储器系统通过与数据信号相同的路径发送自由运行的时钟。 单个时钟域用于读取和写入操作。 对于这两个操作，读或写时钟信号通过与数据相同的传输路径路由，从而通过使数据有效性的窗口最大化来提高系统传输速率。 以这种方式，由于消除了对于选通信号的前导码间隔的需要，数据总线利用率增加，因此存储器模块连接器上的引脚数减少。

公开(公告)号：US20070291575A1

公开(公告)日：2007-12-20

申请号：US11845258

申请日：2007-08-27

申请人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

发明人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

IPC分类号： G11C8/00

CPC分类号： G11C5/00 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/222 ,  G11C8/06 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4093

摘要： A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation. An enable signal may be provided from the memory controller to a second one of the integrated circuit memory devices over a signal line between the memory controller and the second integrated circuit memory device to thereby enable implementation of the mode register set command for the second integrated circuit memory device during the mode register set operation. Moreover, the disable signal may not be provided to the second integrated circuit memory device during the mode register set operation, and the enable signal may not be provided to the first integrated circuit memory device during the mode register set operation. Related systems, devices and additional methods are also discussed.

摘要翻译： 存储器模块可以包括通过相同的命令/地址总线耦合到存储器控制器的多个存储器件。 控制这种存储器模块的方法可以包括在模式寄存器设置操作期间通过命令/地址总线从存储器控制器向每个集成电路存储器件提供模式寄存器设置命令。 可以通过存储器控制器和第一集成电路存储器件之间的信号线从存储器控制器向集成电路存储器件中的第一个提供禁止信号，从而禁止第一集成电路的模式寄存器设置命令的实现 存储器件在模式寄存器设置操作期间。 可以通过存储器控制器和第二集成电路存储器件之间的信号线从存储器控制器向集成电路存储器件中的第二个提供使能信号，从而能够实现第二集成电路的模式寄存器设置命令 存储器件在模式寄存器设置操作期间。 此外，在模式寄存器设置操作期间，禁止信号可能不被提供给第二集成电路存储器件，并且在模式寄存器设置操作期间可以不向第一集成电路存储器件提供使能信号。 还讨论了相关系统，设备和附加方法。

公开(公告)号：US07277356B2

公开(公告)日：2007-10-02

申请号：US11490797

申请日：2006-07-21

申请人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

发明人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

IPC分类号： G11C8/00

CPC分类号： G11C5/00 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/222 ,  G11C8/06 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4093

摘要： A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation. An enable signal may be provided from the memory controller to a second one of the integrated circuit memory devices over a signal line between the memory controller and the second integrated circuit memory device to thereby enable implementation of the mode register set command for the second integrated circuit memory device during the mode register set operation. Moreover, the disable signal may not be provided to the second integrated circuit memory device during the mode register set operation, and the enable signal may not be provided to the first integrated circuit memory device during the mode register set operation. Related systems, devices and additional methods are also discussed.

摘要翻译： 存储器模块可以包括通过相同的命令/地址总线耦合到存储器控制器的多个存储器件。 控制这种存储器模块的方法可以包括在模式寄存器设置操作期间通过命令/地址总线从存储器控制器向每个集成电路存储器件提供模式寄存器设置命令。 可以通过存储器控制器和第一集成电路存储器件之间的信号线从存储器控制器向集成电路存储器件中的第一个提供禁止信号，从而禁止第一集成电路的模式寄存器设置命令的实现 存储器件在模式寄存器设置操作期间。 可以通过存储器控制器和第二集成电路存储器件之间的信号线从存储器控制器向集成电路存储器件中的第二个提供使能信号，从而能够实现第二集成电路的模式寄存器设置命令 存储器件在模式寄存器设置操作期间。 此外，在模式寄存器设置操作期间，禁止信号可能不被提供给第二集成电路存储器件，并且在模式寄存器设置操作期间可以不向第一集成电路存储器件提供使能信号。 还讨论了相关系统，设备和附加方法。

公开(公告)号：US20070087721A1

公开(公告)日：2007-04-19

申请号：US11438223

申请日：2006-05-23

申请人： Jin-soo Park ,  Yong-hun Kim ,  Chang-sik Yoo ,  Seong-Soo Lee ,  Heung-Bae Lee

发明人： Jin-soo Park ,  Yong-hun Kim ,  Chang-sik Yoo ,  Seong-Soo Lee ,  Heung-Bae Lee

IPC分类号： H04B1/28

CPC分类号： H03D7/166

摘要： A subharmonic mixer, including an amplification unit for amplifying an input signal using at least one pair of amplification devices connected in parallel and a mixing unit for mixing the amplified signal with local oscillation signals from local oscillators is provided. The mixing unit performs switching over the amplification devices and at least four pairs of switching devices connected in parallel with each other, two pairs of switching devices being connected in parallel with each other and performing switching over one amplification device. The switching devices are supplied with local oscillation signals having different phases respectively, and two switching devices forming a pair are connected in parallel with each other and supplied with local oscillation signals having a 180° phase difference therebetween. Accordingly, the switching stage is formed with one stage, the operation is enabled with low-voltage power supplies, and noise performance, linearity, and gain are enhanced.

摘要翻译： 提供了一种次谐波混频器，其包括用于使用并联连接的至少一对放大装置放大输入信号的放大单元和用于将放大的信号与来自本地振荡器的本地振荡信号混合的混合单元。 混合单元对放大装置进行切换，并且至少四对开关装置彼此并联连接，两对开关装置彼此并联并执行一个放大装置的切换。 为开关器件分别提供具有不同相位的本地振荡信号，并且形成一对的两个开关器件彼此并联连接并且提供与它们之间具有180°相位差的本地振荡信号。 因此，开关级形成为一级，通过低压电源实现动作，提高噪声性能，线性度和增益。

公开(公告)号：US20060262611A1

公开(公告)日：2006-11-23

申请号：US11490797

申请日：2006-07-21

申请人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

发明人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

IPC分类号： G11C7/00

CPC分类号： G11C5/00 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/222 ,  G11C8/06 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4093

摘要： A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation. An enable signal may be provided from the memory controller to a second one of the integrated circuit memory devices over a signal line between the memory controller and the second integrated circuit memory device to thereby enable implementation of the mode register set command for the second integrated circuit memory device during the mode register set operation. Moreover, the disable signal may not be provided to the second integrated circuit memory device during the mode register set operation, and the enable signal may not be provided to the first integrated circuit memory device during the mode register set operation. Related systems, devices and additional methods are also discussed.

公开(公告)号：US06940321B2

公开(公告)日：2005-09-06

申请号：US10728630

申请日：2003-12-05

申请人： Nak-Won Heo ,  Chang-Sik Yoo

发明人： Nak-Won Heo ,  Chang-Sik Yoo

IPC分类号： G11C11/40 ,  G11C7/10 ,  G11C7/22 ,  H03B1/00 ,  H03B3/00

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/22

摘要： Provided is a circuit for generating a data strobe signal used in a double data rate (DDR) synchronous semiconductor device. The circuit comprises a first logic unit capable of generating a pull up control signal responsive to first and second clock signals. A second logic unit is capable of generating a pull down signal responsive to the first and second clock signals. A data strobe buffer is capable of generating a data strobe signal responsive to the pull up and pull down control signals, the data strobe signal including a preamble. The first logic unit is capable of generating the preamble responsive to a first pulse of the first clock signal. And the data strobe signal is in a high impedance state responsive to a last pulse of the first clock signal.

摘要翻译： 提供了一种用于产生在双倍数据速率（DDR）同步半导体器件中使用的数据选通信号的电路。 电路包括能够响应于第一和第二时钟信号产生上拉控制信号的第一逻辑单元。 第二逻辑单元能够响应于第一和第二时钟信号产生下拉信号。 数据选通缓冲器能够响应于上拉和下拉控制信号产生数据选通信号，数据选通信号包括前导码。 第一逻辑单元能够响应于第一时钟信号的第一脉冲而产生前导码。 并且数据选通信号响应于第一时钟信号的最后脉冲处于高阻抗状态。

公开(公告)号：US06877079B2

公开(公告)日：2005-04-05

申请号：US10079097

申请日：2002-02-20

申请人： Chang-sik Yoo ,  Kye-hyun Kyung

发明人： Chang-sik Yoo ,  Kye-hyun Kyung

IPC分类号： G06F13/16 ,  G06F12/00 ,  G06F13/42

CPC分类号： G06F13/4273

摘要： A clocking system and method in a point-to-point bus configuration overcomes the limitations of conventional approaches. In one embodiment, the present invention ensures the same phase relationship for the write clock in the write direction for all data transfers between modules, and similarly the same phase relationship for the read clock in the read direction for all data transfers between modules, regardless of module location. In another embodiment, on a given module, all transfers of data between a data buffer and a memory device in both read and write directions are clocked by a read clock signal and a write clock signal that have the same phase relationship and have the same propagation delay as the data bus between the buffer and the memory device.

摘要翻译： 点对点总线配置中的时钟系统和方法克服了常规方法的局限性。 在一个实施例中，本发明确保了用于模块之间的所有数据传输的写方向上的写时钟的相位相位关系，并且类似地，对于在模块之间的所有数据传输的读取方向上的读时钟的相同相位关系，而不管 模块位置。 在另一个实施例中，在给定的模块上，在读取和写入方向上的数据缓冲器和存储器件之间的所有数据传输由读取时钟信号和具有相同相位关系且具有相同传播的写入时钟信号 作为缓冲区和存储设备之间的数据总线的延迟。

公开(公告)号：US06456122B1

公开(公告)日：2002-09-24

申请号：US09899223

申请日：2001-07-06

申请人： Joon-young Park ,  Chang-sik Yoo ,  Kee-wook Jung ,  Won-chan Kim

发明人： Joon-young Park ,  Chang-sik Yoo ,  Kee-wook Jung ,  Won-chan Kim

IPC分类号： G11C706

CPC分类号： H03K3/35613 ,  H03K5/2481 ,  H03K19/01721 ,  H03K19/018528

摘要： An input buffer circuit for transforming pseudo differential input signals into full differential output signals wherein, the input buffer circuit includes a pull-up current source, two pull-down current sources, a differential input portion, and a positive feedback portion. The pull-up current source is formed of two PMOS transistors which are always in an “on” state, and provides an electric current. The two pull-down current sources are each formed of an NMOS transistor, which are always in an on state, and sink a pull-up electric current. The differential input portion is formed of two NMOS transistors, and receives an input signal and a reference signal, respectively. The positive feedback portion is formed of two NMOS transistors, and enlarges a voltage difference between two output terminals of the input circuit using positive feedback.

摘要翻译： 一种用于将伪差分输入信号变换为全差分输出信号的输入缓冲电路，其中，输入缓冲电路包括上拉电流源，两个下拉电流源，差分输入部分和正反馈部分。 上拉电流源由总是处于“导通”状态的两个PMOS晶体管形成，并且提供电流。 两个下拉电流源各自由NMOS晶体管形成，它们总是处于导通状态，并且吸收上拉电流。 差分输入部分由两个NMOS晶体管构成，分别接收输入信号和参考信号。 正反馈部分由两个NMOS晶体管形成，并且使用正反馈放大输入电路的两个输出端之间的电压差。