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    Hybrid metal fully silicided (FUSI) gate
    21.
    发明申请
    Hybrid metal fully silicided (FUSI) gate 有权
    混合金属全硅化（FUSI）门

    公开(公告)号：US20090085126A1

    公开(公告)日：2009-04-02

    申请号：US11863804

    申请日：2007-09-28

    Applicant: Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

    Inventor： Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

    IPC: H01L29/00

    CPC classification number: H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

    Abstract: A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer.

    Abstract translation: 公开了一种用于混合金属全硅化（FUSI）栅极结构的半导体器件和系统。 半导体系统包括PMOS栅极结构，PMOS栅极结构包括第一高k电介质层，P金属层，中间间隙金属层，其中中间间隙金属层形成在高k电介质 层，P金属层和形成在P金属层上的完全硅化物层。 半导体系统还包括NMOS栅极结构，NMOS栅极结构包括第二高k电介质层，完全硅化层和中间间隙金属层，其中中间间隙金属层形成在高kappa 电介质和完全硅化物层。

    Semiconductor Device with Multiple Silicide Regions
    22.
    发明申请
    Semiconductor Device with Multiple Silicide Regions 有权
    具有多个硅化物区域的半导体器件

    公开(公告)号：US20080230844A1

    公开(公告)日：2008-09-25

    申请号：US11688592

    申请日：2007-03-20

    Applicant: Chen-Hua Yu ,  Cheng-Tung Lin ,  Chen-Nan Yeh

    Inventor： Chen-Hua Yu ,  Cheng-Tung Lin ,  Chen-Nan Yeh

    IPC: H01L29/78

    CPC classification number: H01L21/26506 ,  H01L21/28044 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6653

    Abstract: A system and method for forming a semiconductor device with a reduced source/drain extension parasitic resistance is provided. An embodiment comprises implanting two metals (such as ytterbium and nickel for an NMOS transistor or platinum and nickel for a PMOS transistor) into the source/drain extensions after silicide contacts have been formed. An anneal is then performed to create a second silicide region within the source/drain extension. Optionally, a second anneal could be performed on the second silicide region to force a further reaction. This process could be performed to multiple semiconductor devices on the same substrate.

    Abstract translation: 提供了一种用于形成具有减小的源极/漏极延伸寄生电阻的半导体器件的系统和方法。 一个实施例包括在形成硅化物接触之后，将两种金属（例如用于NMOS晶体管的镱和镍或用于PMOS晶体管的铂和镍）注入到源极/漏极延伸部中。 然后进行退火以在源极/漏极延伸部内产生第二硅化物区域。 任选地，可以在第二硅化物区域上进行第二退火以迫使进一步的反应。 该过程可以对同一衬底上的多个半导体器件执行。

    Silicide formation with a pre-amorphous implant
    23.
    发明申请
    Silicide formation with a pre-amorphous implant 有权
    具有预非晶态植入物的硅化物形成

    公开(公告)号：US20080070370A1

    公开(公告)日：2008-03-20

    申请号：US11523678

    申请日：2006-09-19

    Applicant: Chii-Ming Wu ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

    Inventor： Chii-Ming Wu ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

    IPC: H01L21/336

    CPC classification number: H01L21/26506 ,  H01L21/2658 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78654

    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, forming a silicon-containing compound stressor adjacent the gate stack, implanting non-siliciding ions into the silicon-containing compound stressor to amorphize an upper portion of the silicon-containing compound stressor, forming a metal layer on the silicon-containing compound stressor while the upper portion of the SiGe stressor is amorphous, and annealing to react the metal layer with the silicon-containing compound stressor to form a silicide region. The silicon-containing compound stressor includes SiGe or SiC.

    Abstract translation: 一种用于形成半导体结构的方法包括：提供半导体衬底，在半导体衬底上形成栅极叠层，在栅堆叠附近形成含硅化合物应力源，将非硅化离子注入到含硅化合物应力器中以使上层 部分含硅化合物应激源，在含硅化合物应激源上形成金属层，同时SiGe应力源的上部为无定形，退火以使金属层与含硅化合物应激源反应形成硅化物区域 。 含硅化合物应激源包括SiGe或SiC。

    Method of forming silicided gate structure
    24.
    发明授权
    Method of forming silicided gate structure 失效
    形成硅化栅结构的方法

    公开(公告)号：US07015126B2

    公开(公告)日：2006-03-21

    申请号：US10859730

    申请日：2004-06-03

    Applicant: Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

    Inventor： Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

    IPC: H01L2132/05

    CPC classification number: H01L21/28097 ,  H01L21/28518 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/785

    Abstract: A method of forming a silicided gate of a field effect transistor on a substrate having active regions is provided. The method includes the following steps: (a) forming a silicide in at least a first portion of a gate; (b) after step (a), depositing a metal over the active regions and said gate; and (c) annealing to cause the metal to react to form silicide in the active regions, wherein the thickness of said gate silicide is greater than the thickness of said silicide in said active regions.

    Abstract translation: 提供了在具有有源区的基板上形成场效应晶体管的硅化物栅的方法。 该方法包括以下步骤：（a）在栅极的至少第一部分中形成硅化物; （b）在步骤（a）之后，在有源区域和所述栅极上沉积金属; 和（c）退火以引起金属反应以在有源区中形成硅化物，其中所述栅极硅化物的厚度大于所述有源区中所述硅化物的厚度。

    Semiconductor device with metal silicides having different phases
    26.
    发明授权
    Semiconductor device with metal silicides having different phases 有权
    具有不同相位的金属硅化物的半导体器件

    公开(公告)号：US08723275B2

    公开(公告)日：2014-05-13

    申请号：US12322118

    申请日：2009-01-27

    Applicant: Wei-Jung Lin ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

    Inventor： Wei-Jung Lin ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

    IPC: H01L29/78

    CPC classification number: H01L21/28097 ,  H01L29/4975 ,  H01L29/517

    Abstract: A fully silicided gate with a selectable work function includes a gate dielectric over the substrate, a first metal silicide layer over the gate dielectric, and a second metal silicide layer wherein the first metal silicide has a different phase then the second metal silicide layer. The metal silicide layers comprises at least one alloy element. The concentration of the alloy element on the interface between the gate dielectric and the metal silicide layers influence the work function of the gate.

    Abstract translation: 具有可选择功函数的完全硅化栅包括在衬底上的栅极电介质，栅极电介质上的第一金属硅化物层和第二金属硅化物层，其中第一金属硅化物具有与第二金属硅化物层不同的相。 金属硅化物层包括至少一种合金元素。 栅极电介质和金属硅化物层之间的界面上的合金元素的浓度影响栅极的功函数。

    Hybrid metal fully silicided (FUSI) gate
    29.
    发明授权
    Hybrid metal fully silicided (FUSI) gate 有权
    混合金属全硅化（FUSI）门

    公开(公告)号：US07745890B2

    公开(公告)日：2010-06-29

    申请号：US11863804

    申请日：2007-09-28

    Applicant: Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

    Inventor： Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

    IPC: H01L29/78

    CPC classification number: H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

    Abstract: A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer.

    Abstract translation: 公开了一种用于混合金属全硅化（FUSI）栅极结构的半导体器件和系统。 所述半导体系统包括PMOS栅极结构，所述PMOS栅极结构包括第一高<！ - SIPO < 介电层，P金属层，中间间隙金属层，其中中间间隙金属层形成在高金属层之间。 电介质层，P金属层和形成在P金属层上的完全硅化物层。 所述半导体系统还包括NMOS栅极结构，所述NMOS栅极结构包括第二高<！ - SIPO < 电介质层，完全硅化物层和中间间隙金属层，其中中间间隙金属层形成在高介电层之间。 电介质和完全硅化物层。

    Self-Aligned Halo/Pocket Implantation for Reducing Leakage and Source/Drain Resistance in MOS Devices
    30.
    发明申请
    Self-Aligned Halo/Pocket Implantation for Reducing Leakage and Source/Drain Resistance in MOS Devices 有权
    用于降低MOS器件泄漏和源极/漏极电阻的自对准光晕/口袋植入

    公开(公告)号：US20090233410A1

    公开(公告)日：2009-09-17

    申请号：US12048119

    申请日：2008-03-13

    Applicant: Chen-Hua Yu ,  Yihang Chiu ,  Shu-Tine Yang ,  Jyh-Cherng Sheu ,  Chu-Yun Fu ,  Cheng-Tung Lin

    Inventor： Chen-Hua Yu ,  Yihang Chiu ,  Shu-Tine Yang ,  Jyh-Cherng Sheu ,  Chu-Yun Fu ,  Cheng-Tung Lin

    IPC: H01L21/336

    CPC classification number: H01L29/7848 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate, wherein the semiconductor substrate and a sidewall of the gate dielectric has a joint point; forming a gate electrode over the gate dielectric; forming a mask layer over the semiconductor substrate and the gate electrode, wherein a first portion of the mask layer adjacent the joint point is at least thinner than a second portion of the mask layer away from the joint point; after the step of forming the mask layer, performing a halo/pocket implantation to introduce a halo/pocket impurity into the semiconductor substrate; and removing the mask layer after the halo/pocket implantation.

    Abstract translation: 一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极电介质，其中所述半导体衬底和所述栅极电介质的侧壁具有接合点; 在所述栅极电介质上形成栅电极; 在所述半导体衬底和所述栅极电极上形成掩模层，其中所述掩模层的与所述接合点相邻的第一部分至少比所述掩模层的离开所述接合点的第二部分更薄; 在形成掩模层的步骤之后，进行晕/穴注入以将卤素/杂质杂质引入到半导体衬底中; 并且在光晕/口袋植入之后去除掩模层。

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