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    CIGS solar cell structure and method for fabricating the same
    1.
    发明授权
    CIGS solar cell structure and method for fabricating the same 有权
    CIGS太阳能电池结构及其制造方法

    公开(公告)号：US09018032B2

    公开(公告)日：2015-04-28

    申请号：US13445997

    申请日：2012-04-13

    Applicant: Hsuan-Sheng Yang ,  Wen-Chin Lee ,  Li-Huan Chu

    Inventor： Hsuan-Sheng Yang ,  Wen-Chin Lee ,  Li-Huan Chu

    IPC: H01L21/00 ,  H01L21/02 ,  H01L31/032 ,  H01L31/0749

    CPC classification number: H01L21/02491 ,  H01L21/02568 ,  H01L21/02614 ,  H01L31/0322 ,  H01L31/0749 ,  Y02E10/541 ,  Y02P70/521

    Abstract: A method for manufacturing a CIGS thin film photovoltaic device includes forming a back contact layer on a substrate, forming an Se-rich layer on the back contact layer, forming a precursor layer on the Se-rich layer by depositing copper, gallium and indium resulting in a first interim structure, annealing or selenizing the first interim structure, thereby forming Cu/Se, Ga/Se or CIGS compounds along the interface between the back contact layer and the precursor layer and resulting in a second interim structure, and selenizing the second interim structure, thereby converting the precursor layer into a CIGS absorber layer on the back contact layer.

    Abstract translation: 一种制造CIGS薄膜光伏器件的方法包括在衬底上形成背接触层，在背接触层上形成富硒层，通过沉积铜，镓和铟在富硒层上形成前体层，从而形成 在第一中间结构中，对第一中间结构进行退火或硒化，从而沿着背接触层和前体层之间的界面形成Cu / Se，Ga / Se或CIGS化合物，并产生第二中间结构，并将第二中间结构 从而将前体层转化为背接触层上的CIGS吸收层。

    Keyboard Having a Key-In Area Integrated with a Touch Sensor Device and a Method Thereof
    2.
    发明申请
    Keyboard Having a Key-In Area Integrated with a Touch Sensor Device and a Method Thereof 审中-公开
    具有与触摸传感器装置集成的键入区域的键盘及其方法

    公开(公告)号：US20130234939A1

    公开(公告)日：2013-09-12

    申请号：US13686857

    申请日：2012-11-27

    Applicant: WEN-CHIN LEE ,  POLOSTAR TECHNOLOGY CORPORATION

    Inventor： WEN-CHIN LEE

    IPC: G06F3/02

    CPC classification number: G06F3/0213

    Abstract: The present invention is related to a keyboard having a key-in area integrated with a touch sensor device and a method thereof by providing at least one touch sensor device at a key location within the key-in area of a keyboard main body, and electrically connecting the touch sensor device to the keyboard main body to transmit a signal via the keyboard main body. With the method of integrating a key-in area of a keyboard with a touch sensor device provided by the present invention, the keyboard and the pointing device can be integrated altogether as one such that the operation and control efficiency thereof is advantageously enhanced and is adapted for various application environments and practical usages.

    Abstract translation: 本发明涉及具有与触摸传感器装置集成的键入区域的键盘及其方法，该方法通过在键盘主体的键入区域内的键位置处提供至少一个触摸传感器装置，并且电气地 将触摸传感器装置连接到键盘主体以经由键盘主体传送信号。 通过将键盘的键入区域与由本发明提供的触摸传感器装置集成的方法，键盘和指示装置可以一体化为一体，使得其操作和控制效率有利地被增强并被适配 适用于各种应用环境和实际应用。

    Contact barrier structure and manufacturing methods
    5.
    发明授权
    Contact barrier structure and manufacturing methods 有权
    接触屏障结构及制造方法

    公开(公告)号：US08030210B2

    公开(公告)日：2011-10-04

    申请号：US12722247

    申请日：2010-03-11

    Applicant: Ching-Ya Wang ,  Chung-Hu Ke ,  Wen-Chin Lee

    Inventor： Ching-Ya Wang ,  Chung-Hu Ke ,  Wen-Chin Lee

    IPC: H01L21/3205

    CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/76844 ,  H01L21/7685 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric (ILD) over the metal layer; and a contact opening in the ILD. The metal layer is exposed through the contact opening. The metal layer further extends under the ILD. The semiconductor structure further includes a contact in the contact opening.

    Abstract translation: 半导体结构包括半导体衬底; 半导体衬底上的栅极电介质; 位于栅极电介质上的栅电极; 与栅极电介质相邻的源极/漏极区域; 源/漏区上的硅化物区; 硅化物区域的顶部和物理接触处的金属层; 金属层上的层间电介质（ILD）; 和ILD的接触开口。 金属层通过接触开口露出。 金属层进一步在ILD下延伸。 半导体结构还包括接触开口中的接触。

    CMOS Devices with Schottky Source and Drain Regions
    6.
    发明申请
    CMOS Devices with Schottky Source and Drain Regions 有权
    具有肖特基源和漏极区域的CMOS器件

    公开(公告)号：US20110223727A1

    公开(公告)日：2011-09-15

    申请号：US13113530

    申请日：2011-05-23

    Applicant: Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

    Inventor： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

    IPC: H01L21/8238

    CPC classification number: H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/47 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/66643 ,  H01L29/7843

    Abstract: A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device is reduced by forming the PMOS device over a semiconductor layer having a low valence band.

    Abstract translation: 半导体结构包括半导体衬底和在半导体衬底的表面处的NMOS器件，其中NMOS器件包括肖特基源极/漏极延伸区域。 半导体结构还包括在半导体衬底的表面处的PMOS器件，其中PMOS器件包括仅包含非金属材料的源极/漏极延伸区域。 可以为PMOS器件和NMOS器件形成肖特基源极/漏极延伸区域，其中通过在具有低价带的半导体层上形成PMOS器件来减小PMOS器件的肖特基势垒高度。

    Metal stress memorization technology
    7.
    发明授权
    Metal stress memorization technology 有权
    金属应力记忆技术

    公开(公告)号：US07985652B2

    公开(公告)日：2011-07-26

    申请号：US11855701

    申请日：2007-09-14

    Applicant: Chung-Hu Ke ,  Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

    Inventor： Chung-Hu Ke ,  Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

    IPC: H01L21/8234

    CPC classification number: H01L21/823807 ,  H01L29/665 ,  H01L29/7847

    Abstract: A semiconductor device and method for manufacturing a tensile strained NMOS and a compressive strained PMOS transistor pair, wherein a stressor material is sacrificial is disclosed. The method provides for a substrate, which includes a source/drain for an NMOS transistor, and a PMOS transistor. A first barrier layer is formed on the substrate and a first stressor material is formed on the first barrier layer. The first barrier layer is selectively removed from the PMOS transistor. The substrate is flash annealed and the remaining first stressor material and barrier layer is removed from the substrate.

    Abstract translation: 公开了用于制造拉伸应变NMOS和压缩应变PMOS晶体管对的半导体器件和方法，其中应力源材料是牺牲的。 该方法提供了一种衬底，其包括用于NMOS晶体管的源极/漏极和PMOS晶体管。 在基板上形成第一阻挡层，在第一阻挡层上形成第一应力源材料。 从PMOS晶体管选择性地去除第一势垒层。 衬底被闪光退火，剩余的第一应力材料和阻挡层从衬底上去除。

    BiCMOS performance enhancement by mechanical uniaxial strain and methods of manufacture
    9.
    发明授权
    BiCMOS performance enhancement by mechanical uniaxial strain and methods of manufacture 有权
    通过机械单轴应变的BiCMOS性能提高和制造方法

    公开(公告)号：US07803718B2

    公开(公告)日：2010-09-28

    申请号：US12260674

    申请日：2008-10-29

    Applicant: Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

    Inventor： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

    IPC: H01L23/31

    CPC classification number: H01L21/8249 ,  H01L21/823807 ,  H01L27/0623 ,  H01L29/7843

    Abstract: A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.

    Abstract translation: 提供了通过机械单轴应变增强性能的BiCMOS器件。 本发明的第一实施例包括形成在衬底的不同区域上的NMOS晶体管，PMOS晶体管和双极晶体管。 具有拉伸应力的第一接触蚀刻停止层形成在NMOS晶体管上，并且在PMOS晶体管和双极晶体管上形成具有压应力的第二接触蚀刻停止层，从而允许每个器件的增强。 除了应力接触蚀刻停止层之外，另一实施例还包括PMOS晶体管和NMOS晶体管中的应变通道区域以及BJT中的应变基极。

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