Self-aligned halo/pocket implantation for reducing leakage and source/drain resistance in MOS devices
    1.
    发明授权
    Self-aligned halo/pocket implantation for reducing leakage and source/drain resistance in MOS devices 有权
    自对准晕圈/凹穴注入,用于减少MOS器件中的漏电和源极/漏极电阻

    公开(公告)号:US08822293B2

    公开(公告)日:2014-09-02

    申请号:US12048119

    申请日:2008-03-13

    Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate, wherein the semiconductor substrate and a sidewall of the gate dielectric has a joint point; forming a gate electrode over the gate dielectric; forming a mask layer over the semiconductor substrate and the gate electrode, wherein a first portion of the mask layer adjacent the joint point is at least thinner than a second portion of the mask layer away from the joint point; after the step of forming the mask layer, performing a halo/pocket implantation to introduce a halo/pocket impurity into the semiconductor substrate; and removing the mask layer after the halo/pocket implantation.

    Abstract translation: 一种形成半导体结构的方法包括:提供半导体衬底; 在所述半导体衬底上形成栅极电介质,其中所述半导体衬底和所述栅极电介质的侧壁具有接合点; 在所述栅极电介质上形成栅电极; 在所述半导体衬底和所述栅极电极上形成掩模层,其中所述掩模层的与所述接合点相邻的第一部分至少比所述掩模层的离开所述接合点的第二部分更薄; 在形成掩模层的步骤之后,进行晕/穴注入以将卤素/杂质杂质引入到半导体衬底中; 并且在光晕/口袋植入之后去除掩模层。

    Advanced metal gate method and device
    3.
    发明授权
    Advanced metal gate method and device 有权
    先进的金属门法和器件

    公开(公告)号:US07799628B2

    公开(公告)日:2010-09-21

    申请号:US12354558

    申请日:2009-01-15

    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a high-k dielectric over a substrate, forming a first metal layer over the high-k dielectric, forming a second metal layer over the first metal layer, forming a first silicon layer over the second metal layer, implanting a plurality of ions into the first silicon layer and the second metal layer overlying a first region of the substrate, forming a second silicon layer over the first silicon layer, patterning a first gate structure over the first region and a second gate structure over a second region, performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively, and driving the ions toward an interface of the first metal layer and the high-k dielectric in the first gate structure.

    Abstract translation: 本公开提供一种制造半导体器件的方法,其包括在衬底上形成高k电介质,在高k电介质上形成第一金属层,在第一金属层上形成第二金属层,形成第一硅 在所述第二金属层上方,将多个离子注入到所述第一硅层中,并且所述第二金属层覆盖在所述基板的第一区域上,在所述第一硅层上形成第二硅层,在所述第一区上形成第一栅极结构 以及在第二区域上的第二栅极结构,执行使所述第二金属层与所述第一硅层反应以在所述第一和第二栅极结构中分别形成硅化物层的退火处理,并将所述离子驱动到 第一栅极结构中的第一金属层和高k电介质。

    Silicide formation with a pre-amorphous implant
    7.
    发明授权
    Silicide formation with a pre-amorphous implant 有权
    具有预非晶态植入物的硅化物形成

    公开(公告)号:US07625801B2

    公开(公告)日:2009-12-01

    申请号:US11523678

    申请日:2006-09-19

    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, forming a silicon-containing compound stressor adjacent the gate stack, implanting non-siliciding ions into the silicon-containing compound stressor to amorphize an upper portion of the silicon-containing compound stressor, forming a metal layer on the silicon-containing compound stressor while the upper portion of the SiGe stressor is amorphous, and annealing to react the metal layer with the silicon-containing compound stressor to form a silicide region. The silicon-containing compound stressor includes SiGe or SiC.

    Abstract translation: 一种用于形成半导体结构的方法包括:提供半导体衬底,在半导体衬底上形成栅极叠层,在栅堆叠附近形成含硅化合物应力源,将非硅化离子注入到含硅化合物应力器中以使上层 含硅化合物应激源的部分,在含硅化合物应激物上形成金属层,同时SiGe应力源的上部是无定形的,退火使金属层与含硅化合物应激反应物形成硅化物区域 。 含硅化合物应激源包括SiGe或SiC。

    Methods for forming MOS devices with metal-inserted polysilicon gate stack
    8.
    发明申请
    Methods for forming MOS devices with metal-inserted polysilicon gate stack 有权
    用金属插入多晶硅栅极叠层形成MOS器件的方法

    公开(公告)号:US20080299754A1

    公开(公告)日:2008-12-04

    申请号:US11809337

    申请日:2007-05-31

    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a metal-containing layer on the gate dielectric; and forming a composite layer over the metal-containing layer. The step of forming the composite layer includes forming an un-doped silicon layer substantially free from p-type and n-type impurities; and forming a silicon layer adjoining the un-doped silicon layer. The step of forming the silicon layer comprises in-situ doping a first impurity. (or need to be change to: forming a silicon layer first & then forming un-doped silicon layer) The method further includes performing an annealing to diffuse the first impurity in the silicon layer into the un-doped silicon layer.

    Abstract translation: 一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质上形成含金属层; 并在该含金属层上形成复合层。 形成复合层的步骤包括形成基本上不含p型和n型杂质的未掺杂硅层; 以及形成邻近所述未掺杂硅层的硅层。 形成硅层的步骤包括原位掺杂第一杂质。 (或者需要改变为:首先形成硅层,然后形成未掺杂的硅层)。该方法还包括执行退火以将硅层中的第一杂质扩散到未掺杂的硅层中。

    Method to improve thermal stability of silicides with additives
    9.
    发明申请
    Method to improve thermal stability of silicides with additives 审中-公开
    提高添加剂硅化物热稳定性的方法

    公开(公告)号:US20060246720A1

    公开(公告)日:2006-11-02

    申请号:US11117152

    申请日:2005-04-28

    CPC classification number: H01L21/28518

    Abstract: A semiconductor method of manufacture involving suicides is provided. Embodiments comprise forming a stacked arrangement of layers, the stacked arrangement of layers comprising an additive layer on a substrate, and a metal layer on the additive layer, annealing the stacked arrangement of layers to form a metal silicide layer on the substrate, wherein the metal silicide layer includes an additive from the additive layer. Alternative embodiments include etching the stacked arrangement of layers to remove an unreacted material layer. In an alternative embodiment, the stacked arrangement of layer comprises a metal layer on a substrate, an additive layer on the metal layer, and an optional oxygen barrier layer on the additive layer. An annealing process forms a metal silicide containing an additive. Metal silicides formed according to embodiments are particularly resistant to agglomeration during high temperature processing.

    Abstract translation: 提供涉及自杀的半导体制造方法。 实施例包括形成层的堆叠布置,在衬底上包括添加层的层的堆叠排列以及添加层上的金属层,退火层的层叠布置以在衬底上形成金属硅化物层,其中金属 硅化物层包括来自添加剂层的添加剂。 替代实施例包括蚀刻层的堆叠布置以去除未反应的材料层。 在替代实施例中,层的堆叠布置包括在基底上的金属层,金属层上的添加层和在添加剂层上的任选的氧阻隔层。 退火工艺形成含有添加剂的金属硅化物。 根据实施例形成的金属硅化物特别耐高温处理期间的附聚。

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