公开(公告)号：US5895237A

公开(公告)日：1999-04-20

申请号：US775177

申请日：1996-12-31

Applicant: Tsiu Chiu Chan ,  Pervez H. Sagarwala

Inventor： Tsiu Chiu Chan ,  Pervez H. Sagarwala

IPC: H01L21/76 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/76216 ,  H01L21/823878

Abstract: A high performance CMOS process using grown field oxide for active area isolation takes advantage of process steps used in LDD transistor fabrication to reduce the chip space occupied by the field oxide. Portions of the spacer oxide layer are retained intact over the field oxide during the etching step used to form the oxide spacers on the sides of the polysilicon gates. The retained spacer oxide portions increase the total oxide thickness in the field area to effectively block the ion implantation used to form the heavily doped portions of the source and drain regions. This enables use, in the initial fabrication steps, of a grown field oxide of reduced thickness and advantageously a correspondingly reduced width so as to reduce the chip space allocated to the field oxide.

Abstract translation: 使用生长场氧化物用于有源面积隔离的高性能CMOS工艺利用LDD晶体管制造中使用的工艺步骤来减少由场氧化物占据的芯片空间。 在用于在多晶硅栅极的侧面上形成氧化物间隔物的蚀刻步骤期间，间隔氧化物层的一部分完整地保留在场氧化物上。 保留的间隔氧化物部分增加了场区域中的总氧化物厚度，以有效地阻止用于形成源极和漏极区域的重掺杂部分的离子注入。 这使得能够在初始制造步骤中使用厚度减小的生长场氧化物，并且有利地相应地减小宽度，以便减少分配给场氧化物的芯片空间。

公开(公告)号：US5889713A

公开(公告)日：1999-03-30

申请号：US891284

申请日：1997-07-10

Applicant: Tsiu Chiu Chan ,  Lawrence P. Eng

Inventor： Tsiu Chiu Chan ,  Lawrence P. Eng

IPC: G06F12/16 ,  G06F11/22 ,  G06F11/273 ,  G06F15/78 ,  G11C29/02 ,  G11C29/44 ,  G11C29/48 ,  G11C7/00

CPC classification number: G06F11/2733 ,  G11C29/48

Abstract: A method and circuits for coupling a memory embedded in an integrated circuit to interconnect pads during a memory test mode is disclosed. The integrated circuit contains a processor, an embedded memory and a switching circuit for: (1) temporary coupling the interconnect pads of the integrated circuit, coupled to the processor during normal operation mode of the circuit, to the memory during a memory test mode; (2) and decoupling the external interconnect pads from the memory, after the memory is tested, and coupling them to the processor.

Abstract translation: 公开了一种在存储器测试模式期间将嵌入在集成电路中的存储器耦合到互连焊盘的方法和电路。 集成电路包含处理器，嵌入式存储器和开关电路，用于：（1）在存储器测试模式期间将集成电路的互连焊盘临时耦合到存储器，所述集成电路的互连焊盘在电路的正常操作模式期间耦合到处理器; （2），并在存储器测试之后将外部互连焊盘与存储器分离，并将其耦合到处理器。

公开(公告)号：US5885871A

公开(公告)日：1999-03-23

申请号：US903608

申请日：1997-07-31

Applicant: Tsiu Chiu Chan ,  Pervez H. Sagarwala ,  Loi Nguyen

Inventor： Tsiu Chiu Chan ,  Pervez H. Sagarwala ,  Loi Nguyen

IPC: H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/66825 ,  H01L29/42324 ,  H01L29/7883 ,  H01L27/115

Abstract: A memory cell for an EEPROM memory is fabricated to provide increased oxide thickness at the edge of the tunnel oxide and under the edges of the polysilicon capacitor plate in order to improve the dielectric integrity of the capacitor structure. In one embodiment using a silicided polysilicon process, the oxide is made thicker at the edge of the tunnel oxide by reoxidizing the silicon at the corner of the polysilicon capacitor plate and the underlying substrate surface by exposing the device to a short duration oxidation step after having deposited a 200 .ANG. to 500 .ANG. thick porous oxide over the device to protect the silicide from excessivie exposure to the oxidizing ambient. In another embodiment the tunnel oxide is grown in a window in the gate oxide layer, which is about four times thicker than the tunnel oxide, so that the gate oxide completely surrounds the tunnel oxide, and the polysilicon capacitor plate extends beyond the edge of the tunnel oxide terminating at a point above the gate oxide.

Abstract translation: 制造用于EEPROM存储器的存储单元以在隧道氧化物的边缘处和在多晶硅电容器板的边缘下方提供增加的氧化物厚度，以便改善电容器结构的电介质完整性。 在使用硅化多晶硅工艺的一个实施例中，通过在多晶硅电容器板和下面的衬底表面的拐角处再氧化硅，使隧道氧化物的边缘处的氧化物变得更厚，所述氧化物在具有 在器件上沉积500 ANGSTROM厚度为500的多孔氧化物，以保护硅化物免受暴露于氧化环境的过量。 在另一个实施例中，隧道氧化物在栅极氧化物层的窗口中生长，其大约是隧道氧化物的厚度的四倍，使得栅极氧化物完全围绕隧道氧化物，并且多晶硅电容器板延伸超过 隧道氧化物终止于栅极氧化物上方的一点。

公开(公告)号：US5883544A

公开(公告)日：1999-03-16

申请号：US758930

申请日：1996-12-03

Applicant: Jason Siucheong So ,  Tsiu Chiu Chan

Inventor： Jason Siucheong So ,  Tsiu Chiu Chan

IPC: H01L21/8234 ,  G05F3/24 ,  H01L27/088 ,  H03K17/30 ,  H03K19/094

CPC classification number: G05F3/242

Abstract: An integrated circuit includes a plurality of MOSFETs having channels of a first conductivity type, and having active control of an effective threshold voltage of the MOSFETs to be less than an absolute value of an initial threshold voltage. In this embodiment, a first MOSFET has a channel of the first conductivity type, and a second MOSFET is connected to the first MOSFET and has a channel of a second conductivity type. The second MOSFET is preferably biased to a pinch-off region and cooperates with the first MOSFET for generating a control signal related to an effective threshold voltage of the first MOSFET. Moreover, the circuit preferably generates a bias voltage to the plurality of MOSFETs and to the first MOSFET based upon the control signal to set an effective threshold voltage of the plurality of MOSFETs to have an absolute value less than an absolute value of the initial threshold voltage and, more preferably, to a reference voltage. Accordingly, lower supply voltages can be readily accommodated. In another embodiment, the biasing is only provided to activated circuit portions.

Abstract translation: 集成电路包括具有第一导电类型的沟道的多个MOSFET，并且将MOSFET的有效阈值电压的主动控制小于初始阈值电压的绝对值。 在本实施例中，第一MOSFET具有第一导电类型的沟道，第二MOSFET连接到第一MOSFET并且具有第二导电类型的沟道。 第二MOSFET优选地被偏置到夹断区域并与第一MOSFET配合以产生与第一MOSFET的有效阈值电压相关的控制信号。 此外，电路优选地基于控制信号向多个MOSFET和第一MOSFET产生偏置电压，以将多个MOSFET的有效阈值电压设置为具有小于初始阈值电压的绝对值的绝对值 并且更优选地参考参考电压。 因此，可以容易地适应较低的电源电压。 在另一个实施例中，偏置仅被提供给激活的电路部分。

公开(公告)号：US5849614A

公开(公告)日：1998-12-15

申请号：US652904

申请日：1996-05-23

Applicant: Tsiu Chiu Chan

Inventor： Tsiu Chiu Chan

IPC: H01L21/76 ,  H01L21/336 ,  H01L21/761 ,  H01L21/765 ,  H01L27/08 ,  H01L27/118 ,  H01L29/78 ,  H01L21/763

CPC classification number: H01L21/76 ,  H01L21/761 ,  H01L21/765 ,  H01L27/11807

Abstract: An isolation gate structure is formed between active areas on a P-type semiconductor substrate. The isolation structure includes a thick gate oxide layer over which is formed a P-doped polycrystalline silicon layer. The polycrystalline silicon layer is electrically connected to the substrate, by buried contact if desired, and can further be electrically connected to a source region formed within the active area. The polycrystalline silicon layer and substrate are connected to ground potential, thus preventing current flow between active areas.

Abstract translation: 在P型半导体衬底上的有源区之间形成隔离栅极结构。 隔离结构包括厚栅氧化层，其上形成P掺杂多晶硅层。 如果需要，多晶硅层通过埋入接触电连接到衬底，并且还可以电连接到形成在有源区域内的源极区域。 多晶硅层和衬底连接到地电势，从而防止有源区之间的电流流动。

公开(公告)号：US5834966A

公开(公告)日：1998-11-10

申请号：US770548

申请日：1996-12-08

Applicant: Jason Siucheong So ,  Tsiu Chiu Chan

Inventor： Jason Siucheong So ,  Tsiu Chiu Chan

IPC: H01L21/8234 ,  G05F3/20 ,  G05F3/24 ,  G11C5/14 ,  H01L27/088 ,  H03K17/30

CPC classification number: G11C5/146 ,  G05F3/205 ,  G05F3/247

Abstract: An integrated circuit includes a plurality of MOSFETs on a substrate. A plurality of sensing MOSFETs are used to generate a plurality of comparison signals based upon comparing signals related to the sensed initial threshold voltages to respective reference voltages from a spread of high to low reference voltage values. The MOSFETs are biased to have a desired effective threshold voltage based upon the plurality of comparison signals. Logic decoding circuits accept the plurality of comparison signals and generate at least one bias control signal. Bias circuits are responsive to the at least one bias control signal for generating a desired bias voltage from among a plurality of bias voltages having a spread of high to low bias voltage values to thereby bias the plurality of MOSFETs to the desired effective threshold voltage. Method aspects of the invention are also disclosed.

Abstract translation: 集成电路包括在衬底上的多个MOSFET。 使用多个感测MOSFET来产生多个比较信号，所述比较信号基于从感测到的初始阈值电压与从高到低基准电压值的扩展到相应参考电压的相关信号。 基于多个比较信号，MOSFET被偏置成具有期望的有效阈值电压。 逻辑解码电路接受多个比较信号并产生至少一个偏置控制信号。 偏置电路响应于至少一个偏置控制信号，用于从具有高到低偏置电压值的扩展的多个偏置电压之间产生期望的偏置电压，从而将多个MOSFET偏置到期望的有效阈值电压。 还公开了本发明的方法方面。

公开(公告)号：US5821600A

公开(公告)日：1998-10-13

申请号：US704153

申请日：1996-08-28

Applicant: Tsiu Chiu Chan

Inventor： Tsiu Chiu Chan

IPC: H01L21/76 ,  H01L21/336 ,  H01L21/761 ,  H01L21/765 ,  H01L27/08 ,  H01L27/118 ,  H01L29/78 ,  H01L29/00 ,  H01L29/76

CPC classification number: H01L21/76 ,  H01L21/761 ,  H01L21/765 ,  H01L27/11807

Abstract: An isolation gate structure is formed between active areas on a P-type semiconductor substrate. The isolation structure includes a thick gate oxide layer over which is formed a P-doped polycrystalline silicon layer. The polycrystalline silicon layer is electrically connected to the substrate, by buried contact if desired, and can further be electrically connected to a source region formed within the active area. The polycrystalline silicon layer and substrate are connected to ground potential, thus preventing current flow between active areas.

Abstract translation: 在P型半导体衬底上的有源区之间形成隔离栅极结构。 隔离结构包括厚栅氧化层，其上形成P掺杂多晶硅层。 如果需要，多晶硅层通过埋入接触电连接到衬底，并且还可以电连接到形成在有源区域内的源极区域。 多晶硅层和衬底连接到地电势，从而防止有源区之间的电流流动。

公开(公告)号：US5798278A

公开(公告)日：1998-08-25

申请号：US681065

申请日：1996-07-22

Applicant: Tsiu Chiu Chan ,  Gregory C. Smith

Inventor： Tsiu Chiu Chan ,  Gregory C. Smith

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/265 ,  H01L29/76

CPC classification number: H01L29/6659 ,  H01L21/28518 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/66628 ,  H01L29/7833

Abstract: A method is provided for forming a planar transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A transistor encapsulated in a dielectric is formed over a substrate. First source and drain regions are formed in the substrate adjacent the transistor. Conductive raised second source and drain regions are formed which overly exposed portions of the first substrate source and drain regions adjacent the transistor. The raised second source and drain regions are formed such that an upper surface of the raised second source and drain regions are substantially planar with an upper surface of the transistor. The dielectric encapsulating the transistor electrically isolates the transistor from the raised second source and drain regions.

Abstract translation: 提供一种用于形成半导体集成电路的平面晶体管的方法和根据该集成电路形成的集成电路。 封装在电介质中的晶体管形成在衬底上。 第一源区和漏区形成在与晶体管相邻的衬底中。 形成导电隆起的第二源极和漏极区，其中与第一衬底源极和漏极区域相邻的过度暴露部分与晶体管相邻。 凸起的第二源极和漏极区域被形成为使得凸起的第二源极和漏极区域的上表面与晶体管的上表面基本上是平面的。 封装晶体管的电介质将晶体管与升高的第二源极和漏极区电隔离。

公开(公告)号：US5707014A

公开(公告)日：1998-01-13

申请号：US415654

申请日：1995-04-03

Applicant: Ying-Chiu Chan ,  Daniel Lo ,  Kenneth Hung Kwan Ma

Inventor： Ying-Chiu Chan ,  Daniel Lo ,  Kenneth Hung Kwan Ma

IPC: B05B1/20 ,  B08B3/02 ,  B60S3/04 ,  B05B3/00

CPC classification number: B60S3/042 ,  B08B3/02 ,  B08B3/026 ,  B05B1/20

Abstract: A water jet cleaner for the underside of a vehicle. A plurality of jets are directed upwardly from a spray head which is mounted on a longitudinal member positioned closely to the ground on which the vehicle is resting. A handle is attached to the longitudinal member and wheels are mounted to the frame and the longitudinal member to allow manual reciprocal movement of the cleaner beneath the vehicle by an operator. The jets are angularly adjustable such that the cleaner may also be used to clean the surface itself such as a driveway.

Abstract translation: 一种用于车辆底面的喷水清洁器。 多个喷嘴从喷头向上引导，该喷头安装在靠近车辆静止的地面的纵向构件上。 手柄连接到纵向构件，并且轮子安装到框架和纵向构件，以允许操作者手动地将清洁器倒置在车辆下方。 喷射器是可角度调节的，使得清洁器也可以用于清洁表面本身，例如车道。

公开(公告)号：US5670424A

公开(公告)日：1997-09-23

申请号：US542815

申请日：1995-10-13

Applicant: Tsiu Chiu Chan ,  Frank Randolph Bryant ,  John Leonard Walters

Inventor： Tsiu Chiu Chan ,  Frank Randolph Bryant ,  John Leonard Walters

IPC: H01L21/768 ,  H01L23/532 ,  H01L27/11 ,  H01L21/44

CPC classification number: H01L23/53271 ,  H01L21/76889 ,  H01L21/76895 ,  H01L27/1104 ,  H01L2924/0002 ,  Y10S148/039 ,  Y10S257/903

Abstract: An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.

Abstract translation: 互连结构及其形成方法适用于诸如SRAM器件的集成电路。 该结构使用多晶硅互连电平的掩模将P-N结移动到多晶硅互连线内的区域，而不是在衬底处。 然后可以使用形成在多晶硅互连结构上的难熔金属硅化物来短路该P-N结。