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    Capacitor-based digital-to-analog converter with continuous time output
    21.
    发明授权
    Capacitor-based digital-to-analog converter with continuous time output 失效
    具有连续时间输出的基于电容器的数/模转换器

    公开(公告)号：US06271784B1

    公开(公告)日：2001-08-07

    申请号：US08909650

    申请日：1997-08-12

    Applicant: Lapoe E. Lynn ,  Paul F. Ferguson, Jr. ,  Hae-Seung Lee

    Inventor： Lapoe E. Lynn ,  Paul F. Ferguson, Jr. ,  Hae-Seung Lee

    IPC: H03M166

    CPC classification number: H03M1/0872 ,  H03M1/804

    Abstract: A digital-to-analog converter (DAC) including an array of switched input capacitors which store samples of charge proportional to a digital input signal, and an analog output circuit which integrates the samples of charge to generate an output analog signal that is proportional to said digital input signal. The capacitors store a binary representation of the digital input signal. The output circuit includes a zeroth order sample-and-hold circuit having first and second stages with respective first and second operational amplifiers. The first and second stages are cascaded together during a sample phase so that the analog output signal is stored in a capacitor in a feedback path between the output of the second stage and the input of the first stage, and are disconnected from one another during a hold phase so that the first stage is auto-zeroed and the second stage holds the analog output signal as a continuous time output.

    Abstract translation: 包括存储与数字输入信号成比例的电荷样本的开关式输入电容阵列的数模转换器（DAC），以及模拟输出电路，其对电荷采样进行积分，以产生与 所述数字输入信号。 电容器存储数字输入信号的二进制表示。 输出电路包括具有第一和第二级的第零级采样和保持电路，其具有相应的第一和第二运算放大器。 第一级和第二级在采样阶段级联在一起，使得模拟输出信号被存储在第二级的输出和第一级的输入之间的反馈路径中的电容器中，并且在一个 保持相位使得第一级自动归零，第二级将模拟输出信号保持为连续时间输出。

    Split parity spare disk achieving method in raid subsystem
    22.
    发明授权
    Split parity spare disk achieving method in raid subsystem 失效
    分区奇偶备用磁盘实现方法在raid子系统中

    公开(公告)号：US6070249A

    公开(公告)日：2000-05-30

    申请号：US935201

    申请日：1997-09-22

    Applicant: Hae-Seung Lee

    Inventor： Hae-Seung Lee

    IPC: G06F12/16 ,  G06F3/06 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G11B19/02 ,  G11B20/18

    CPC classification number: G06F11/1076

    Abstract: A split parity spare disk achieving method for improving the defect endurance and performance of a RAID subsystem which distributively stores data in a disk array consisting of a plurality of disk drives and carries out an input/output operation in parallel includes the steps of: constructing the disk array with at least two data disk drives for storing data, a spare disk drive used when a disk drive fails and a parity disk drive for storing parity data; and splitting the parity data of the parity disk drive and storing the split data in the parity disk drive and the spare disk drive.

    Abstract translation: 一种用于提高分散存储在由多个磁盘驱动器组成的磁盘阵列中的数据并且并行执行输入/输出操作的RAID子系统的缺陷耐久性和性能的分裂奇偶校验备用磁盘实现方法包括以下步骤： 具有用于存储数据的至少两个数据磁盘驱动器的磁盘阵列，当磁盘驱动器发生故障时使用的备用磁盘驱动器和用于存储奇偶校验数据的奇偶校验磁盘驱动器; 以及分割奇偶校验磁盘驱动器的奇偶校验数据并将分割数据存储在奇偶校验磁盘驱动器和备用磁盘驱动器中。

    Algorithmic A/D converter with digitally calibrated output
    23.
    发明授权
    Algorithmic A/D converter with digitally calibrated output 失效
    具有数字校准输出的算法A / D转换器

    公开(公告)号：US5510789A

    公开(公告)日：1996-04-23

    申请号：US412269

    申请日：1995-03-28

    Applicant: Hae-Seung Lee

    Inventor： Hae-Seung Lee

    IPC: H03M1/10 ,  H03M1/44

    CPC classification number: H03M1/1038 ,  H03M1/442

    Abstract: A multistage pipelined algorithmic A/D converter digitally calibrated to avoid errors due to charge injection, offset and capacitor mismatch. To perform this calibration, measurements are made at the converter to determine the degree of capacitor mismatch for each stage to be calibrated. In the embodiment disclosed, only one stage is calibrated. The remaining stages of the converter are employed to develop the digital calibration data for the stage being measured. This calibration data is stored in a memory forming part of the converter. The stored data is thereafter used during each conversion to cancel the errors due to capacitor mismatch.

    Abstract translation: 多级流水线算法A / D转换器进行数字校准，以避免由于电荷注入，偏移和电容器失配引起的错误。 要执行此校准，在转换器进行测量以确定要校准的每个级的电容器失配程度。 在所公开的实施例中，仅校准一个级。 采用转换器的剩余阶段来开发待测阶段的数字校准数据。 该校准数据存储在形成转换器的一部分的存储器中。 之后在每次转换期间使用存储的数据来消除由于电容器失配引起的误差。

    Analog-to-digital conversion circuit with improved differential linearity
    24.
    发明授权
    Analog-to-digital conversion circuit with improved differential linearity 失效
    具有改进差分线性度的模数转换电路

    公开(公告)号：US5416485A

    公开(公告)日：1995-05-16

    申请号：US170040

    申请日：1993-12-20

    Applicant: Hae-Seung Lee

    Inventor： Hae-Seung Lee

    IPC: H03M1/06 ,  H03M1/16 ,  H03M1/80 ,  H03M1/44

    CPC classification number: H03M1/066 ,  H03M1/167 ,  H03M1/804

    Abstract: An analog-to-digital converter having at least one stage, each stage comprising an array of capacitors, one or more comparators, an operational amplifier, and switches. Each stage operates in two phases, the sampling phase and the amplifying phase. During the sampling phase, the input voltage is sampled on the capacitor array. During the amplifying phase, one plate of each capacitors is connected to the reference voltage, ground, or the output of the operational amplifier to produce a residue voltage. Each of the array is sequentially connected to the output of the operational amplifier as the input voltage increases. The resulting residue drop for each digital code increase is precisely equal to the full-scale voltage. Combined with over-range and digital error-correction, the resulting A/D converter exhibits excellent differential linearity.

    Abstract translation: 具有至少一个级的模数转换器，每级包括电容器阵列，一个或多个比较器，运算放大器和开关。 每个阶段分两个阶段进行，采样阶段和放大阶段。 在采样阶段，在电容阵列上对输入电压进行采样。 在放大阶段期间，每个电容器的一个板被连接到参考电压，地或运算放大器的输出端以产生残余电压。 当输入电压增加时，阵列中的每一个依次连接到运算放大器的输出。 每个数字代码增加的结果残留量下降精确地等于满量程电压。 结合超范围和数字纠错，得到的A / D转换器表现出优异的差分线性度。

    Merged bipolar and insulated gate transistors
    25.
    发明授权
    Merged bipolar and insulated gate transistors 失效
    合并双极和绝缘栅晶体管

    公开(公告)号：US5028977A

    公开(公告)日：1991-07-02

    申请号：US367387

    申请日：1989-06-16

    Applicant: K. O. Kenneth ,  Hae-Seung Lee ,  L. Rafael Reif

    Inventor： K. O. Kenneth ,  Hae-Seung Lee ,  L. Rafael Reif

    IPC: H01L27/07

    CPC classification number: H01L27/0716

    Abstract: A vertical bipolar transistor is formed along with an IGFET transistor in a process in which the bipolar transistor collector, base and emitter structure is formed in the body of a semiconductor mesa-like structure while the IGFET transistor is formed in and along one of the sidewalls of the structure. Source and drain regions are formed in the structure by ion-implantation using a polysilicon gate electrode formed over a gate insulator on the sidewall as a self-aligning mask.

    Abstract translation: 在双极晶体管集电极，基极和发射极结构形成在半导体台面状结构体中的过程中，与IGFET晶体管一起形成垂直双极晶体管，同时IGFET晶体管沿着侧壁 的结构。 通过使用在侧壁上的栅绝缘体上形成的多晶硅栅极作为自对准掩模，通过离子注入在该结构中形成源区和漏区。

    2-phase threshold detector based circuits
    27.
    发明授权
    2-phase threshold detector based circuits 有权
    基于2相阈值检测器的电路

    公开(公告)号：US08432192B2

    公开(公告)日：2013-04-30

    申请号：US13112275

    申请日：2011-05-20

    Applicant: Matthew Guyton ,  Hae-Seung Lee

    Inventor： Matthew Guyton ,  Hae-Seung Lee

    IPC: H03K5/22

    CPC classification number: H03M1/56 ,  H03M1/162

    Abstract: A switched capacitor circuit includes a threshold detector to generate a threshold detection signal when a difference between first and second input signals crosses a predetermined level. A coarse current source produces a coarse ramp. A series sampling capacitor samples a coarse output voltage when the threshold detector indicates a first threshold crossing. The sampling capacitor is connected in series with a fine current source producing a fine ramp.

    Abstract translation: 开关电容电路包括阈值检测器，用于当第一和第二输入信号之间的差异跨越预定电平时产生阈值检测信号。 粗电流源产生粗斜坡。 当阈值检测器指示第一阈值交叉时，串联采样电容器对粗略的输出电压进行采样。 采样电容器与精细电流源串联连接，产生细微的斜坡。

    Constant slope ramp circuits for sampled-data circuits
    29.
    发明授权
    Constant slope ramp circuits for sampled-data circuits 有权
    用于采样数据电路的恒定斜坡斜坡电路

    公开(公告)号：US08294495B2

    公开(公告)日：2012-10-23

    申请号：US12484489

    申请日：2009-06-15

    Applicant: Hae-Seung Lee

    Inventor： Hae-Seung Lee

    IPC: H03K4/06

    CPC classification number: H03K17/56 ,  G11C27/024

    Abstract: A circuit includes a level-crossing detector to generate a level-crossing detection signal when an input signal crosses a predetermined voltage level. A first stage set of capacitors is operatively coupled to the level-crossing detector. A ramp circuit is operatively coupled to the set of series-connected capacitors. A second stage set of capacitors is operatively coupled to the first stage set of capacitors and the ramp circuit. The ramp circuit includes a feedback capacitor and a preset switch to provide a linear ramp output.

    Abstract translation: 电路包括电平交叉检测器，用于当输入信号跨越预定电压电平时产生电平交叉检测信号。 第一级电容器可操作地耦合到电平交叉检测器。 斜坡电路可操作地耦合到该组串联电容器。 第二级电容器可操作地耦合到第一级电容器组和斜坡电路。 斜坡电路包括反馈电容器和预设开关以提供线性斜坡输出。

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