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    NOVEL LAYOUT ARCHITECTURE FOR PERFORMANCE ENHANCEMENT
    21.
    发明申请
    NOVEL LAYOUT ARCHITECTURE FOR PERFORMANCE ENHANCEMENT 审中-公开
    性能增强的新型布局架构

    公开(公告)号：US20100127333A1

    公开(公告)日：2010-05-27

    申请号：US12276172

    申请日：2008-11-21

    Applicant: Yung-Chin Hou ,  Ta-Pen Guo ,  Harry Chuang ,  Carlos H. Diaz ,  Lee-Chung Lu ,  Li-Chun Tien ,  Oscar M. K. Law ,  Chih-Chiang Chang ,  Chun-Hui Tai ,  Jonathan Lee

    Inventor： Yung-Chin Hou ,  Ta-Pen Guo ,  Harry Chuang ,  Carlos H. Diaz ,  Lee-Chung Lu ,  Li-Chun Tien ,  Oscar M. K. Law ,  Chih-Chiang Chang ,  Chun-Hui Tai ,  Jonathan Lee

    IPC: H01L27/092 ,  H01L27/088

    CPC classification number: H01L27/0207 ,  H01L21/823418 ,  H01L21/823481

    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes an active region in a semiconductor substrate; a first field effect transistor (FET) disposed in the active region; and an isolation structure disposed in the active region. The FET includes a first gate; a first source formed in the active region and disposed on a first region adjacent the first gate from a first side; and a first drain formed in the active region and disposed on a second region adjacent the first gate from a second side. The isolation structure includes an isolation gate disposed adjacent the first drain; and an isolation source formed in the active region and disposed adjacent the isolation gate such that the isolation source and the first drain are on different sides of the isolation gate.

    Abstract translation: 本发明提供集成电路。 集成电路包括半导体衬底中的有源区; 设置在有源区中的第一场效应晶体管（FET） 以及设置在有源区域中的隔离结构。 FET包括第一栅极; 形成在所述有源区中并且从第一侧设置在与所述第一栅极相邻的第一区域上的第一源极; 以及形成在所述有源区中并且从第二侧设置在与所述第一栅极相邻的第二区域上的第一漏极。 隔离结构包括邻近第一漏极设置的隔离栅极; 以及隔离源，形成在所述有源区中并邻近所述隔离栅设置，使得所述隔离源和所述第一漏极位于所述隔离栅极的不同侧上。

    Reverse-biased PN diode decoupling capacitor
    22.
    发明授权
    Reverse-biased PN diode decoupling capacitor 有权
    反向偏置PN二极管去耦电容

    公开(公告)号：US07550820B2

    公开(公告)日：2009-06-23

    申请号：US11502094

    申请日：2006-08-10

    Applicant: Hsien-Te Chen ,  Jen-Hang Yang ,  Chun-Hui Tai

    Inventor： Hsien-Te Chen ,  Jen-Hang Yang ,  Chun-Hui Tai

    IPC: H01L29/93

    CPC classification number: H01L29/8611 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0814

    Abstract: This invention discloses a decoupling capacitor in an integrated circuit, comprising a plurality of dedicated PN diodes with a total junction area greater than one tenth of a total active area of functional devices for which the dedicated PN diodes are intended to protect, a N-type region of the dedicated PN diodes coupling to a positive supply voltage (Vdd), and a P-type region of the dedicated PN diodes coupling to a complimentary lower supply voltage (Vss), wherein the dedicated PN diodes are reversely biased.

    Abstract translation: 本发明公开了一种集成电路中的去耦电容器，其包括多个专用PN二极管，其总结面积大于专用PN二极管旨在保护的功能器件的总有效面积的十分之一，N型 耦合到正电源电压（Vdd）的专用PN二极管的区域和耦合到互补的较低电源电压（Vss）的专用PN二极管的P型区域，其中专用PN二极管被反向偏置。

    Synergist for improving crop stress resistance and fertilizer absorption capacity
    24.
    发明授权
    Synergist for improving crop stress resistance and fertilizer absorption capacity 有权

    公开(公告)号：US11246313B2

    公开(公告)日：2022-02-15

    申请号：US16699513

    申请日：2019-11-29

    Applicant: SICHUAN HUI TAI AGRICULTURAL TECHNOLOGY CO. LTD.

    Inventor： Lezhang Chen ,  Junbo Yang

    IPC: A01N63/10 ,  A01N65/26 ,  C05G5/12 ,  C05G3/60 ,  A01N25/12 ,  A01N59/06 ,  A01N59/16 ,  A01N63/00

    Abstract: The invention discloses a synergist for improving crop resistance and fertilizer absorption capacity. The synergist includes the following components by weight: 20-30 parts of an oyster shell powder, 20-30 parts of a water chestnut skin powder, 10-20 parts of a chinaberry bark powder, 10-20 parts of a magnetic material, 10-20 parts of an illite powder, 5-10 parts of a shiitake mushroom polysaccharide extract. The synergist can, on one hand, improve the resistance of crops, especially reducing the pests and diseases significantly, improving waterlogging and drought resistance; and, on the other hand, greatly reduce the use of fertilizers, especially nitrogen fertilizers, preventing soil compaction. It can also significantly increase the content of active polysaccharides, especially β-glucan in crops. In addition, the raw materials are readily available, the cost is low, and there are significant economic benefits.

    AGRICULTURAL PRODUCT FOR IMPROVING IMMUNITY
    25.
    发明申请
    AGRICULTURAL PRODUCT FOR IMPROVING IMMUNITY 审中-公开

    公开(公告)号：US20200221663A1

    公开(公告)日：2020-07-16

    申请号：US16734513

    申请日：2020-01-06

    Applicant: SICHUAN HUI TAI AGRICULTURAL TECHNOLOGY CO. LTD.

    Inventor： Lezhang CHEN ,  Junbo YANG

    IPC: A01H6/46 ,  A01H5/10 ,  A01N63/32 ,  A01N59/16 ,  A01C1/06

    Abstract: A method of producing an agricultural product for improving immunity, the agriculture product being rice, includes: (1) soaking seeds of the agricultural product in a solution containing a magnetic material and a β-glucan; (2) before planting the seeds, applying a bottom fertilizer to a paddy field for the agricultural product, the bottom fertilizer including an organic fertilizer, the magnetic material, an oyster shell powder, the (3-glucan and an organic zinc; and (3) at tillering stage, applying a topdressing to the paddy filed, the topdressing including the β-glucan and the organic zinc.

    Integrated Circuit Design using DFM-Enhanced Architecture
    29.
    发明申请
    Integrated Circuit Design using DFM-Enhanced Architecture 有权
    使用DFM增强架构的集成电路设计

    公开(公告)号：US20100281446A1

    公开(公告)日：2010-11-04

    申请号：US12708242

    申请日：2010-02-18

    Applicant: Yung-Chin Hou ,  Lee-Chung Lu ,  Li-Chun Tien ,  Yi-Kan Cheng ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Yuan-Te Hou

    Inventor： Yung-Chin Hou ,  Lee-Chung Lu ,  Li-Chun Tien ,  Yi-Kan Cheng ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Yuan-Te Hou

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    Abstract: Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell.

    Abstract translation: 集成电路库包括具有第一左边界和第一右边界的第一标准单元，以及具有第二左边界和第二右边界的第二标准单元。 第一标准细胞和第二标准细胞具有相同的细胞变体。 第一标准单元中的第一有源区具有与第二标准单元中的第二有源区不同的扩散长度。 第一有源区和第二有源区是由表示第一标准单元和第二标准单元的相同电路图的相同分量表示的相应有源区。

    Layout architecture for improving circuit performance
    30.
    发明授权
    Layout architecture for improving circuit performance 有权
    用于提高电路性能的布局架构

    公开(公告)号：US07821039B2

    公开(公告)日：2010-10-26

    申请号：US12193354

    申请日：2008-08-18

    Applicant: Li-Chun Tien ,  Lee-Chung Lu ,  Yung-Chin Hou ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Sheng-Hsin Chen ,  Ping Chung Li

    Inventor： Li-Chun Tien ,  Lee-Chung Lu ,  Yung-Chin Hou ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Sheng-Hsin Chen ,  Ping Chung Li

    IPC: H01L27/10 ,  H01L23/62 ,  H01L29/76 ,  H01L29/94 ,  H01L29/00

    CPC classification number: H01L27/092 ,  H01L27/0207

    Abstract: An integrated circuit structure includes an integrated circuit structure including a PMOS transistor including a first gate electrode; a first source region; and a first drain region; an NMOS transistor including a second gate electrode, wherein the first gate electrode and the second gate electrode are portions of a gate electrode strip; a second source region; and a second drain region. No additional transistors are formed between the PMOS transistor and the NMOS transistor. The integrated circuit further includes a VDD power rail connected to the first source region; a VSS power rail connected to the second source region; and an interconnection port electrically connected to the gate electrode strip. The interconnection port is on an outer side of a MOS pair region including the PMOS transistor, the NMOS transistor, and the region between the PMOS transistor and the NMOS transistor. The portion of the gate electrode strip in the MOS pair region is substantially straight.

    Abstract translation: 集成电路结构包括集成电路结构，其包括：包括第一栅电极的PMOS晶体管; 第一源区; 和第一漏区; 包括第二栅电极的NMOS晶体管，其中所述第一栅电极和所述第二栅电极是栅电极条的部分; 第二源区; 和第二漏区。 在PMOS晶体管和NMOS晶体管之间不会形成附加的晶体管。 集成电路还包括连接到第一源极区的VDD电源轨; 连接到第二源区的VSS电力轨; 以及电连接到栅电极条的互连端口。 互连端口位于包括PMOS晶体管，NMOS晶体管以及PMOS晶体管和NMOS晶体管之间的区域的MOS对区域的外侧。 MOS对区域中的栅电极条的部分基本上是直的。

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