公开(公告)号：US20090072322A1

公开(公告)日：2009-03-19

申请号：US11961551

申请日：2007-12-20

Applicant: Sung-Bok Lee ,  Joon-Hee Lee

Inventor： Sung-Bok Lee ,  Joon-Hee Lee

IPC: H01L27/105

CPC classification number: H01L27/11568 ,  H01L27/0207 ,  H01L27/115

Abstract: Semiconductor devices are provided. A semiconductor device can include a substrate and a plurality of dummy line patterns on the substrate that extend in a first direction parallel with one another. Each of the dummy line patterns can include a plurality of sub-line patterns aligned along the first direction and which are separated from each other by at least one cutting region therebetween. The dummy line patterns can include first and second dummy line patterns which are adjacent to each other in a second direction that is perpendicular to the first direction. At least one of the cutting regions between a pair of sub-line patterns of the first dummy line pattern is aligned with and bounded by one of the sub-line patterns of the second dummy line pattern in the second direction.

Abstract translation: 提供半导体器件。 半导体器件可以包括衬底和在基板上的彼此平行的第一方向上延伸的多个虚拟线图案。 虚线图案中的每一个可以包括沿着第一方向排列的多个子线图案，并且通过其间的至少一个切割区域彼此分离。 假线图案可以包括在垂直于第一方向的第二方向上彼此相邻的第一和第二假线图案。 第一伪线图案的一对子线图案之间的切割区域中的至少一个与第二虚线图案的第二方向上的一条子线图案对准并限定在第二方向上。

公开(公告)号：US20080237679A1

公开(公告)日：2008-10-02

申请号：US12133146

申请日：2008-06-04

Applicant: Jong-Sun Sel ,  Jung-Dal Choi ,  Joon-Hee Lee ,  Hwa-Kyung Shin

Inventor： Jong-Sun Sel ,  Jung-Dal Choi ,  Joon-Hee Lee ,  Hwa-Kyung Shin

IPC: H01L29/423 ,  H01L21/336

CPC classification number: H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11529

Abstract: A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern and a sidewall conductive patter. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.

Abstract translation: 公开了一种栅极图案，其包括半导体衬底，下导电图案，上导电图案和侧壁导电图案。 下导电图案在基板上。 绝缘图案位于下导电图案上。 上导电图案位于与下导电图案相对的绝缘图案上。 侧壁导电图案位于上导电图案和下导电图案的侧壁的至少一部分上。 侧壁导电图形电连接上导电图案和下导电图案。 下导电图案的上边缘部分可以相对于下导电图案的下边缘部分凹进，以在其上限定凸缘。 侧壁导电图案可以直接在下导电图案的凹陷的上边缘部分的凸缘和侧壁上。

公开(公告)号：US20080175081A1

公开(公告)日：2008-07-24

申请号：US12007518

申请日：2008-01-11

Applicant: Byoung-Sul Kim ,  Joon Hee Lee ,  Jae In Song ,  Jun-Ho Jo

Inventor： Byoung-Sul Kim ,  Joon Hee Lee ,  Jae In Song ,  Jun-Ho Jo

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C11/4094 ,  G11C7/1042 ,  G11C11/4076

Abstract: A semiconductor memory device and an operation control method thereof are provided. The method may comprise executing a control such that a precharge operating mode and an active operating mode may be successively performed in response to one pre-active command, thereby reducing the current consumption and loading of the system, and thus, enhancing system performance.

Abstract translation: 提供半导体存储器件及其操作控制方法。 该方法可以包括执行控制，使得响应于一个预先活动命令可以连续执行预充电操作模式和主动操作模式，从而减少系统的电流消耗和负载，从而提高系统性能。

公开(公告)号：US20070195718A1

公开(公告)日：2007-08-23

申请号：US11601692

申请日：2006-11-20

Applicant: Ju-han Lee ,  Seung-gi Chang ,  Joon-hee Lee ,  Jun-hae Choi ,  In-hwan Kim ,  Ji-hoon Kim ,  Ho-Jeong You

Inventor： Ju-han Lee ,  Seung-gi Chang ,  Joon-hee Lee ,  Jun-hae Choi ,  In-hwan Kim ,  Ji-hoon Kim ,  Ho-Jeong You

IPC: H04L12/16 ,  H04L12/56

CPC classification number: H04B3/542 ,  H04B2203/5408 ,  H04B2203/5445 ,  H04B2203/545 ,  H04L12/185 ,  H04L12/2801

Abstract: A method of transmitting data more effectively, and more particularly, a method of transmitting data to a group comprising a plurality of reception stations that receive the same data from a transmission station when the stations communicate the data in a power line communication (PLC) network, and an apparatus to do the same. According to the method, a transmission station transmits data to a group including a plurality of reception stations that receive the same data at a time, to prevent a channel bandwidth from being wasted, and to prevent a station that does not desire to receive the data from receiving the data.

Abstract translation: 一种更有效地发送数据的方法，更具体地说，一种方法，当站在电力线通信（PLC）网络中传送数据时，将数据发送到包括从发送站接收相同数据的多个接收站的组 ，以及进行相同操作的装置。 根据该方法，发送站将数据发送到包含一次接收相同数据的多个接收站的组，以防止信道带宽被浪费，并且防止不希望接收数据的站 从接收数据。

公开(公告)号：US07246280B2

公开(公告)日：2007-07-17

申请号：US11086059

申请日：2005-03-22

Applicant: Youn-Cheul Kim ,  Hee-Joo Choi ,  Kae-Won Ha ,  Joon-Hee Lee

Inventor： Youn-Cheul Kim ,  Hee-Joo Choi ,  Kae-Won Ha ,  Joon-Hee Lee

IPC: G11C29/00

CPC classification number: G11C29/40 ,  G11C29/28 ,  G11C2029/2602

Abstract: Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X test data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of test data bits from a plurality of memory blocks. In addition, each comparison unit outputs test data bits from one of the memory blocks within the respective memory chip.

Abstract translation: 存储器模块的每个存储器芯片测试来自X个存储器块的总共N个数据位用于有效测试，并从其中一个存储器块输出N / X个测试数据位。 存储器模块包括多个存储器芯片和多个比较单元。 每个比较单元设置在相应的存储器芯片内，用于从多个存储器块测试多个测试数据位。 此外，每个比较单元从相应的存储器芯片内的一个存储器块输出测试数据位。

公开(公告)号：US20070138867A1

公开(公告)日：2007-06-21

申请号：US11582960

申请日：2006-10-19

Applicant: Jun-hae Choi ,  In-hwan Kim ,  Seung-gi Chang ,  Joon-hee Lee ,  Ju-han Lee ,  Ji-hoon Kim ,  Ho-jeong You

Inventor： Jun-hae Choi ,  In-hwan Kim ,  Seung-gi Chang ,  Joon-hee Lee ,  Ju-han Lee ,  Ji-hoon Kim ,  Ho-jeong You

IPC: H02J3/02 ,  G05B11/01 ,  G08B1/08

CPC classification number: H02J13/0048 ,  Y02B90/263 ,  Y04S40/123

Abstract: Provided is an apparatus for adjusting the phase difference between different phases in a power line communication (PLC) system. The apparatus includes a power signal blocking unit blocking a power signal and allowing a data signal to pass between two different phases on three-phase power lines; and a data signal delaying unit delaying the data signal by the phase difference between the two different phases. Accordingly, it is possible to prevent data collision and a time delay in data transmission between different phases by employing the phase adjusting apparatus in a PLC system, thereby improving the performance of PLC.

Abstract translation: 提供了一种用于调整电力线通信（PLC）系统中的不同相位之间的相位差的装置。 该装置包括电源信号阻断单元，其阻断功率信号并允许数据信号在三相电力线上的两个不同相之间通过; 以及数据信号延迟单元，通过两个不同相位之间的相位差延迟数据信号。 因此，可以通过在PLC系统中采用相位调整装置来防止数据冲突和不同相位之间的数据传输的时间延迟，从而提高PLC的性能。

公开(公告)号：US20070093063A1

公开(公告)日：2007-04-26

申请号：US11585713

申请日：2006-10-24

Applicant: Hyun-Suk Kim ,  Won-Jin Kim ,  Joon-Hee Lee ,  Yong-Seok Kim ,  Jong-Won Kim

Inventor： Hyun-Suk Kim ,  Won-Jin Kim ,  Joon-Hee Lee ,  Yong-Seok Kim ,  Jong-Won Kim

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/3212 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11531

Abstract: There is provided a method of chemical mechanical polishing (CMP) and a method of fabricating a semiconductor device using the same. The method includes forming a layer to be polished on a semiconductor substrate including a normally polished region and a dished region, and forming a dishing (i.e., over-polishing)-preventing layer on the layer to be polished in the region where dishing may occur. Then, the layer to be polished is polished while dishing thereof is prevented using the dishing-preventing layer. Accordingly, the dishing-preventing layer is formed in the region where the dishing (i.e., over-polishing) may occur, so that the dishing is prevented from occurring in a region where pattern density is low and a pattern size is large in the process of CMP.

Abstract translation: 提供了化学机械抛光（CMP）的方法和使用其的半导体器件的制造方法。 该方法包括在包括正常抛光区域和碟形区域的半导体衬底上形成待抛光层，并且在可能发生凹陷的区域中在待抛光层上形成凹陷（即，过抛光） - 预防层 。 然后，使用防止凹陷层防止要抛光的层，同时使其抛光。 因此，在可能发生凹陷（即，过度抛光）的区域中形成凹陷防止层，从而防止在图案密度低的区域和图案尺寸在该过程中发生凹陷 的CMP。

公开(公告)号：US20060093966A1

公开(公告)日：2006-05-04

申请号：US11241458

申请日：2005-09-30

Applicant: Jong-Sun Sel ,  Jung-Dal Choi ,  Joon-Hee Lee ,  Hwa-Kyung Shin

Inventor： Jong-Sun Sel ,  Jung-Dal Choi ,  Joon-Hee Lee ,  Hwa-Kyung Shin

IPC: G03F7/00

CPC classification number: H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11529

Abstract: A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.

Abstract translation: 公开了一种栅极图案，其包括半导体衬底，下导电图案，上导电图案和侧壁导电图案。 下导电图案在基板上。 绝缘图案位于下导电图案上。 上导电图案位于与下导电图案相对的绝缘图案上。 侧壁导电图案位于上导电图案和下导电图案的侧壁的至少一部分上。 侧壁导电图形电连接上导电图案和下导电图案。 下导电图案的上边缘部分可以相对于下导电图案的下边缘部分凹进，以在其上限定凸缘。 侧壁导电图案可以直接在下导电图案的凹陷的上边缘部分的凸缘和侧壁上。

公开(公告)号：US06518642B2

公开(公告)日：2003-02-11

申请号：US09878118

申请日：2001-06-06

Applicant: Hong-Soo Kim ,  Joon-Hee Lee

Inventor： Hong-Soo Kim ,  Joon-Hee Lee

IPC: H01L2900

CPC classification number: H01L21/76802 ,  H01L21/3185 ,  H01L21/76838 ,  H01L23/5258 ,  H01L27/0629 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invented method and device provide a reliable contact to a passive device of a semiconductor circuit device, the passive device being, for example, a resistor, an inductor, a fuse or the like. Adjacent, spaced, elevated, so-called dummy pattern (shoulder) regions are formed under the portions of the passive device on which the contact hole is formed. The shoulder region is formed of the same material as the first conductive layer of the gate of the peripheral transistor. The electrode may be formed through the contact hole to be a reliable contact to the integrated passive device.

公开(公告)号：US10014315B2

公开(公告)日：2018-07-03

申请号：US15589528

申请日：2017-05-08

Applicant: Hyun-suk Kim ,  Joon-hee Lee ,  Kee-jeong Rho

Inventor： Hyun-suk Kim ,  Joon-hee Lee ,  Kee-jeong Rho

IPC: H01L27/11573 ,  H01L49/02 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11521 ,  H01L27/11568

CPC classification number: H01L27/11573 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11582 ,  H01L28/60 ,  H01L28/91

Abstract: Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity. The device includes a substrate having a cell region and a peripheral circuit region, a memory cell string including a plurality of vertical memory cells formed in the cell region and channel holes formed to penetrate the vertical memory cells in a first direction vertical to the substrate, an insulating layer formed in the peripheral circuit region on the substrates at substantially the same level as an upper surface of the memory cell string, and a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, the plurality of capacitor electrodes extending parallel to the channel holes. The plurality of capacitor electrodes are spaced apart from one another in a second direction parallel to the substrate, and the insulating layer is interposed between a pair of adjacent capacitor electrodes from among the plurality of capacitor electrodes.