公开(公告)号：US4344784A

公开(公告)日：1982-08-17

申请号：US238769

申请日：1981-02-27

Applicant: Peter C. Deckas ,  James A. Cooper ,  James V. Leebens, Jr.

Inventor： Peter C. Deckas ,  James A. Cooper ,  James V. Leebens, Jr.

IPC: B01D46/10

CPC classification number: B01D46/10 ,  Y10S55/18 ,  Y10S55/31

Abstract: A filter assembly for clean air installations includes a block of high efficiency particulate air (HEPA) filter material adhesively bonded and sealed within an imperforate rigid thin-walled side frame which extends axially beyond the inlet surface of the filter block and thus provides an integral plenum chamber volume as part of a self-contained filter subassembly. The side frame has peripheral cover and supporting flanges at its inlet and outlet ends and can thus be conveniently assembled with and removed from a reusable cover member and cover gasket for the plenum chamber and a reusable perforated outlet grill and one or more peripheral outlet sealing gaskets, all of which constitute parts of a complete filter assembly which can be readily supported by a standard or special ceiling or wall grid or frame assembly.

Abstract translation: 用于清洁空气装置的过滤器组件包括高效颗粒空气（HEPA）过滤材料块，其粘合并密封在无孔刚性薄壁侧框架内，该侧框架轴向延伸超过过滤器块的入口表面，因此提供了一体的集气室 室容积作为自包含过滤器子组件的一部分。 侧框架在其入口端和出口端具有外围盖和支撑凸缘，因此可以方便地与可重复使用的盖构件组装和移除，并且用于用于增压室的盖垫圈和可重复使用的穿孔出口格栅和一个或多个外围出口密封垫圈 所有这些都构成完整的过滤器组件的一部分，其可以容易地由标准或特殊的天花板或墙壁网格或框架组件支撑。

公开(公告)号：US08945218B2

公开(公告)日：2015-02-03

申请号：US11753889

申请日：2007-05-25

Applicant: Cato T. Laurencin ,  Frank K. Ko ,  James A. Cooper ,  Helen H. Lu ,  Mohammed A. Attawia

Inventor： Cato T. Laurencin ,  Frank K. Ko ,  James A. Cooper ,  Helen H. Lu ,  Mohammed A. Attawia

IPC: A61F2/02 ,  A61F2/44 ,  A61F2/08 ,  A61F2/40 ,  A61F2/38

CPC classification number: A61F2/08 ,  A61F2/38 ,  A61F2/40 ,  A61F2210/0004 ,  A61F2230/0006 ,  A61F2230/0019 ,  A61L27/18 ,  A61L27/56 ,  A61L27/58 ,  A61L2430/10

Abstract: Degradable, polymeric fiber-based, three-dimensional braided scaffolds for use as graft materials in ligament and tendon repair, reconstruction and replacement are provided. Also provided are methods for preparing these scaffolds.

公开(公告)号：US08476697B1

公开(公告)日：2013-07-02

申请号：US13418028

申请日：2012-03-12

Applicant: James A. Cooper ,  Maherin Matin

Inventor： James A. Cooper ,  Maherin Matin

IPC: H01L29/66

CPC classification number: H01L29/7811 ,  H01L21/046 ,  H01L21/0475 ,  H01L29/66068 ,  H01L29/7802 ,  Y10S438/931

Abstract: A silicon carbide power MOSFET having a drain region of a first conductivity type, a base region of a second conductivity type above the drain region, and a source region of the first conductivity type adjacent an upper surface of the base region, the base region including a channel extending from the source region through the base region adjacent a gate interface surface thereof, the channel having a length less than approximately 0.6 μm, and the base region having a doping concentration of the second conductivity type sufficiently high that the potential barrier at the source end of the channel is not lowered by the voltage applied to the drain. The MOSFET includes self-aligned base and source regions as well as self-aligned ohmic contacts to the base and source regions.

Abstract translation: 具有第一导电类型的漏极区域，位于漏极区域之上的第二导电类型的基极区域和与该基极区域的上表面相邻的第一导电类型的源极区域的碳化硅功率MOSFET，所述基极区域包括 从源极区域延伸通过与其栅极界面表面相邻的基极区域的沟道，沟道具有小于约0.6μm的长度，并且具有足够高的第二导电类型的掺杂浓度的基极区域使得在 通道的源极端不被施加到漏极的电压降低。 MOSFET包括自对准的基极和源极区域以及到基极和源极区域的自对准欧姆接触。

公开(公告)号：US08343841B2

公开(公告)日：2013-01-01

申请号：US12961410

申请日：2010-12-06

Applicant: James A. Cooper ,  Xiaokun Wang

Inventor： James A. Cooper ,  Xiaokun Wang

IPC: H01L21/331

CPC classification number: H01L29/7395

Abstract: A method for fabricating a semiconductor device includes forming a first semiconductor layer on a front side of the semiconductor substrate. Additional semiconductor layers may be formed on a font side of the first semiconductor layer. The substrate is subsequently removed. In some embodiments, one or more additional semiconductor layers may be formed on the back side of the first semiconductor layer after the semiconductor substrate has been removed. Additionally, in some embodiments, a portion of the first semiconductor layer is removed along with the semiconductor substrate. In such embodiments, the first semiconductor layer is subsequently etched to a known thickness. Source regions and device electrodes may be then be formed.

Abstract translation: 一种制造半导体器件的方法包括在半导体衬底的前侧形成第一半导体层。 另外的半导体层可以形成在第一半导体层的字体侧上。 随后除去衬底。 在一些实施例中，在去除半导体衬底之后，可以在第一半导体层的背面上形成一个或多个附加的半导体层。 另外，在一些实施例中，第一半导体层的一部分与半导体衬底一起被去除。 在这样的实施例中，第一半导体层随后被蚀刻到已知的厚度。 然后可以形成源区和器件电极。

公开(公告)号：US06362495B1

公开(公告)日：2002-03-26

申请号：US09264156

申请日：1999-03-05

Applicant: Kipp J. Schoen ,  Jason P. Henning ,  Jerry M. Woodall ,  James A. Cooper, Jr. ,  Michael R. Melloch

Inventor： Kipp J. Schoen ,  Jason P. Henning ,  Jerry M. Woodall ,  James A. Cooper, Jr. ,  Michael R. Melloch

IPC: H01L310312

CPC classification number: H01L29/1608 ,  H01L29/47 ,  H01L29/872 ,  H01L31/0312

Abstract: A dual-metal-trench silicon carbide Schottky pinch rectifier having a plurality of trenches formed in an n-type SiC substrate, with a Schottky contact having a relatively low barrier height on a mesa defined between adjacent ones of the trenches, and a Schottky contact having a relatively high barrier height at the bottom of each trench. The same metal used for the Schottky contact in each trench is deposited over the Schottky contact on the mesa. A simplified fabrication process is disclosed in which the high barrier height metal is deposited over the low barrier height metal and then used as an etch mask for reactive ion etching of the trenches to produce a self-aligned low barrier contact.

Abstract translation: 一种双金属沟槽碳化硅肖特基压紧整流器，其具有形成在n型SiC衬底中的多个沟槽，肖特基接触在相邻沟槽之间限定的台面上具有相对较低的势垒高度，以及肖特基接触 在每个沟槽的底部具有较高的势垒高度。 在每个沟槽中用于肖特基接触的相同金属沉积在台面上的肖特基接触件上。 公开了一种简化的制造工艺，其中高阻挡高度金属沉积在低阻挡高度金属上，然后用作蚀刻掩模以用于沟槽的反应离子蚀刻以产生自对准低阻挡接触。

公开(公告)号：US5365477A

公开(公告)日：1994-11-15

申请号：US899538

申请日：1992-06-16

Applicant: James A. Cooper, Jr. ,  Michael R. Melloch ,  Theresa B. Stellwag

Inventor： James A. Cooper, Jr. ,  Michael R. Melloch ,  Theresa B. Stellwag

IPC: H01L27/06 ,  H01L27/102 ,  H01L29/92 ,  H01L29/161

CPC classification number: H01L27/0605 ,  H01L27/1023 ,  H01L29/92

Abstract: A vertically integrated DRAM cell having a storage time of at least 4.5 hours at room temperature, formed from a wide-bandgap semiconductor such as GaAs or AlGaAs, in which an n-p-n bipolar access transistor is merged with a p-n-p storage capacitor, with the middle p-n layers being common to both. Similarly, a p-n-p transistor can be merged with an n-p-n storage capacitor.

Abstract translation: 由GaAs或AlGaAs等宽带隙半导体形成的室温下至少4.5小时的垂直集成DRAM单元，其中npn双极存取晶体管与pnp存储电容器合并，中间pn 两层都是共同的。 类似地，p-n-p晶体管可以与n-p-n存储电容器合并。

公开(公告)号：US4635083A

公开(公告)日：1987-01-06

申请号：US851273

申请日：1986-04-10

Applicant: James A. Cooper, Jr.

Inventor： James A. Cooper, Jr.

IPC: H01L27/06 ,  H01L27/108 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L27/108 ,  H01L27/0605

Abstract: A memory device includes a relative lower bandgap energy first semiconductor layer, a relatively higher bandgap energy second semiconductor layer on the first, an alloy source rectifying to the first layer, a well for storing charge and a gate for controlling charge flow between the source and the well. The gate is formed on the second layer, as is a field plate for controlling the storage charge in the well. In one embodiment, a buried channel field effect transistor is combined with the basic memory device, with the charge content of the well controlling current flow between the source and drain of the buried channel FET.

Abstract translation: 存储器件包括相对较低的带隙能量第一半导体层，第一相对较高的带隙能量第二半导体层，对第一层整流的合金源，用于存储电荷的阱和用于控制源极和 那个井 栅极形成在第二层上，栅极板也用于控制井中的储存电荷。 在一个实施例中，掩埋沟道场效应晶体管与基本存储器件组合，阱控制电流的电荷含量在掩埋沟道FET的源极和漏极之间流动。

公开(公告)号：US4291247A

公开(公告)日：1981-09-22

申请号：US77753

申请日：1979-09-21

Applicant: James A. Cooper, Jr. ,  Robert H. Krambeck

Inventor： James A. Cooper, Jr. ,  Robert H. Krambeck

IPC: H03K19/017 ,  H03K19/096

CPC classification number: H03K19/0963 ,  H03K19/017 ,  H03K19/01728

Abstract: Logic circuits, particularly of the integrated semiconductor type, are accessed at improved speeds by preventing pull-ups from occurring during the access time and by the inclusion of on-chip delay circuitry to avoid switching later stages in a manner to lose information while output nodes of earlier stages are high. All stages are activated in response to a single clock pulse edge.

Abstract translation: 特别是集成半导体类型的逻辑电路通过防止在访问时间期间发生上拉和通过包括片上延迟电路以避免以输出节点丢失信息的方式切换后续阶段而以改进的速度访问 的早期阶段很高。 响应于单个时钟脉冲边沿激活所有级。

公开(公告)号：US4208728A

公开(公告)日：1980-06-17

申请号：US971866

申请日：1978-12-21

Applicant: Donald E. Blahut ,  James A. Cooper, Jr.

Inventor： Donald E. Blahut ,  James A. Cooper, Jr.

IPC: H03K19/177 ,  G11C11/40

CPC classification number: H03K19/1772

Abstract: The decoder portion of a programable logic array (PLA) includes logic devices at crosspoints defined between the word (x) lines and the address (y) lines characteristic of a decoder portion. The devices are operative to combine two or more word lines to activate a single word line in the associated read only memory (ROM) in response to one of two or more possible inputs. The technique is effective even in cases where "don't care" conditions relating the two or more possible inputs cannot be found. A substantial reduction in chip area is achieved.

Abstract translation: 可编程逻辑阵列（PLA）的解码器部分包括在解码器部分的字（x）线和地址（y）线特性之间定义的交叉点处的逻辑器件。 这些装置可操作以组合两个或更多个字线，以响应于两个或多个可能输入中的一个来激活相关联的只读存储器（ROM）中的单个字线。 即使在“无关”条件下，无法找到两个或多个可能输入的情况，该技术也是有效的。 实现了芯片面积的显着降低。