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    Programmable high-resolution timing jitter injectors high-resolution timing jitter injectors
    21.
    发明授权
    Programmable high-resolution timing jitter injectors high-resolution timing jitter injectors 有权
    可编程高分辨率定时抖动注入器高分辨率定时抖动注入器

    公开(公告)号：US07348821B2

    公开(公告)日：2008-03-25

    申请号：US10946709

    申请日：2004-09-22

    Applicant: Jianping Xu ,  KyeHyung Lee ,  Fabrice Paillet ,  David Rennie ,  Tanay Karnik

    Inventor： Jianping Xu ,  KyeHyung Lee ,  Fabrice Paillet ,  David Rennie ,  Tanay Karnik

    IPC: H03H11/26

    CPC classification number: H03K5/1504 ,  H03K5/133 ,  H03K2005/00058

    Abstract: A device includes a first circuit having rows and columns of delay cells to generate delayed signals based on an input signal. The delayed signals are selectable and have a different delay from one another with respect to the input signal. The device is programmable based on a delay code. Different values of the delay code allow the device to select different delayed signals. The device may select one of the delayed signals from the first circuit for use as a timing signal in a second circuit of the device. The device may also use the delayed signals from the first circuit to evaluate a clock and data recovery circuit. In an embodiment, the circuits may be located on a single die.

    Abstract translation: 一种装置包括具有行和列的延迟单元的第一电路，以基于输入信号产生延迟信号。 延迟信号是可选择的并且相对于输入信号具有彼此不同的延迟。 该设备可以基于延迟码进行编程。 延迟码的不同值允许设备选择不同的延迟信号。 设备可以选择来自第一电路的延迟信号之一用作设备的第二电路中的定时信号。 该装置还可以使用来自第一电路的延迟信号来评估时钟和数据恢复电路。 在一个实施例中，电路可以位于单个管芯上。

    DIGITAL SIGNATURE COLLECTION AND AUTHENTICATION
    22.
    发明申请
    DIGITAL SIGNATURE COLLECTION AND AUTHENTICATION 有权
    数字签名收集和认证

    公开(公告)号：US20070242059A1

    公开(公告)日：2007-10-18

    申请号：US11766086

    申请日：2007-06-20

    Applicant: Jianping Xu

    Inventor： Jianping Xu

    IPC: G06F3/033

    CPC classification number: G06K9/00167 ,  G06F3/0346 ,  G06F3/03545 ,  G06F3/043 ,  G06K9/00154 ,  G07C9/0015

    Abstract: A digital signature collection and authentication system includes an ink pen having an ultrasonic transmitter that transmits ultrasonic energy to a plurality of ultrasonic receivers. A computer triangulates the location of the pen versus time to generate the signature shape, and to generate velocity and acceleration data. The pen also includes a pressure sensitive tip to record pressure applied to the pen tip. The pen also includes a higher frequency burst transmitter useful to generate a time reference, and to transmit the pressure information. The computer packetizes the shape, velocity, acceleration, and pressure data with a time stamp and an IP address or phone number, encrypts the packet and sends it to a host computer for authentication.

    Abstract translation: 数字签名收集和认证系统包括具有向超声波接收器发送超声波能量的超声波发射器的墨水笔。 计算机将笔的位置与时间进行三角测量以生成签名形状，并生成速度和加速度数据。 该笔还包括压力敏感的尖端以记录施加到笔尖的压力。 该笔还包括用于产生时间基准的较高频率脉冲串发射器，以及传送压力信息。 计算机使用时间戳和IP地址或电话号码对形状，速度，加速度和压力数据进行打包，对数据包进行加密，并将其发送到主机进行认证。

    0th droop detector architecture and implementation
    23.
    发明申请
    0th droop detector architecture and implementation 有权
    第0个下垂检测器架构和实现

    公开(公告)号：US20070013414A1

    公开(公告)日：2007-01-18

    申请号：US11172250

    申请日：2005-06-30

    Applicant: Fabrice Paillet ,  Tanay Karnik ,  Jianping Xu ,  Vivek De

    Inventor： Fabrice Paillet ,  Tanay Karnik ,  Jianping Xu ,  Vivek De

    IPC: H03K5/00

    CPC classification number: H03K19/00346

    Abstract: A voltage droop detector captures the very high-frequency noise on the power grid of a load, such as a microprocessor. The droop detector includes twin circuits, one of which receives the voltage from the power grid of the load, the other of which receives a filtered voltage. A 0th droop, as well as 1st droops, 2nd droops, and so on, are captured and stored for subsequent analysis. The circuits sample the voltages frequently enough to ensure that all droop events are captured. Other embodiments are described and claimed.

    Abstract translation: 电压下降检测器捕获诸如微处理器的负载的电网上的非常高频噪声。 下垂检测器包括双电路，其中一个接收来自负载的电网的电压，另一个接收经滤波的电压。 捕获并存储第0次下垂以及1次下垂，2次下垂等，以便后续分析。 电路频繁地对电压进行采样，以确保捕获所有下垂事件。 描述和要求保护其他实施例。

    Oscillator delay stage with active inductor
    24.
    发明授权
    Oscillator delay stage with active inductor 失效
    具有有源电感的振荡器延迟级

    公开(公告)号：US07161439B2

    公开(公告)日：2007-01-09

    申请号：US10991976

    申请日：2004-11-18

    Applicant: Fabrice Paillet ,  Tanay Karnik ,  Jianping Xu

    Inventor： Fabrice Paillet ,  Tanay Karnik ,  Jianping Xu

    IPC: H03B5/20

    CPC classification number: H03K3/0322 ,  H03K5/133 ,  H03K2005/00208 ,  H03L7/0995

    Abstract: According to some embodiments, a circuit includes a ring oscillator delay stage. The delay stage may include a first transistor, a second transistor, and an active inductor. A gate of the first transistor may receive a first input signal, a gate of the second transistor may receive a second input signal, a source of the second transistor may be coupled to a source of the first transistor, and the active inductor may be coupled to a drain of the first transistor.

    Abstract translation: 根据一些实施例，电路包括环形振荡器延迟级。 延迟级可以包括第一晶体管，第二晶体管和有源电感器。 第一晶体管的栅极可以接收第一输入信号，第二晶体管的栅极可以接收第二输入信号，第二晶体管的源极可以耦合到第一晶体管的源极，并且有源电感器可以耦合 到第一晶体管的漏极。

    Clock and data recovery circuit
    25.
    发明申请
    Clock and data recovery circuit 审中-公开
    时钟和数据恢复电路

    公开(公告)号：US20060067452A1

    公开(公告)日：2006-03-30

    申请号：US10948697

    申请日：2004-09-24

    Applicant: Jianping Xu ,  Fabrice Paillet ,  Peter Hazucha ,  Tanay Karnik

    Inventor： Jianping Xu ,  Fabrice Paillet ,  Peter Hazucha ,  Tanay Karnik

    IPC: H03D3/24

    CPC classification number: H03L7/091 ,  H04J3/0685 ,  H04L7/0079 ,  H04L7/033

    Abstract: A clock and data recovery circuit is provided that includes a phase/frequency detector to receive input data and multiphase clock signals. The phase/frequency detector including a first set of flip-flop circuits each to sample the input data at one of the multiphase clock signals and each to output a sampled data, and a second set of flip-flop circuits to retime the sampled data based on a similar clock signal applied to each of the second set of flip-flop circuits.

    Abstract translation: 提供了一种时钟和数据恢复电路，其包括用于接收输入数据和多相时钟信号的相位/频率检测器。 相位/频率检测器包括第一组触发器电路，每个触发器电路各自以多相时钟信号中的一个采样输入数据，并且每个触发器电路各自输出采样数据;以及第二组触发器电路，用于基于采样数据进行加权 在施加到每个第二组触发器电路的类似时钟信号上。

    High-speed data sampler for optical interconnect
    27.
    发明申请
    High-speed data sampler for optical interconnect 有权
    用于光互连的高速数据采样器

    公开(公告)号：US20050069070A1

    公开(公告)日：2005-03-31

    申请号：US10673218

    申请日：2003-09-30

    Applicant: Fabrice Paillet ,  Tanay Karnik ,  Jianping Xu

    Inventor： Fabrice Paillet ,  Tanay Karnik ,  Jianping Xu

    IPC: H03L7/081 ,  H04L7/00

    CPC classification number: H04L7/0079 ,  H03L7/0812 ,  H04L7/0008

    Abstract: A system and method for sampling a data stream generates a number of clock signals having equally spaced phases and then samples a data stream using the clock signals. The clock phases are preferably based on a predetermined fraction of a data rate frequency of the data stream, and sampling is performed based on predetermined combinations of the clock signals. While the system and method is suitable for sampling data transmitted for a wide variety of data rates, the system and method is especially well-suited to sampling at data transmitted at high rates, for example, equal to or greater than 20 Gb/s.

    Abstract translation: 用于对数据流进行采样的系统和方法产生具有相等间隔相位的多个时钟信号，然后使用时钟信号对数据流进行采样。 时钟相位优选地基于数据流的数据速率频率的预定分数，并且基于时钟信号的预定组合来执行采样。 虽然系统和方法适合于为各种数据速率传输的数据采样，但是该系统和方法特别适合于以高速率传输的数据进行采样，例如等于或大于20Gb / s。

    Process for hydrogenation of isoalpha acids
    28.
    发明授权
    Process for hydrogenation of isoalpha acids 有权
    异磷酸氢化方法

    公开(公告)号：US06198004B1

    公开(公告)日：2001-03-06

    申请号：US09329299

    申请日：1999-06-10

    Applicant: John Paul Maye ,  Jianping Xu ,  George Gauthier ,  Scott W. Weis

    Inventor： John Paul Maye ,  Jianping Xu ,  George Gauthier ,  Scott W. Weis

    IPC: C07C4567

    CPC classification number: C12C5/026 ,  C12C3/08 ,  C12C3/12 ,  C12C9/025

    Abstract: The invention relates to a process for converting alpha acid and isoalpha acids to tetrahydroisoalpha acid. The process comprises isomerizing an alpha acid to produce isoalpha acid and hydrogenating the isoalpha acid in the presence of a noble metal catalyst wherein, the noble metal catalyst is added incrementally or continuously throughout the hydrogenation step. The invention also relates to tetrahydroisoalpha acids made by the above process.

    Abstract translation: 本发明涉及将α-酸和异α-酸转化为四氢异α酸的方法。 该方法包括异构化α酸以产生异α酸并在贵金属催化剂存在下氢化异α酸，其中贵金属催化剂在整个氢化步骤中逐渐或连续地加入。 本发明还涉及通过上述方法制备的四氢异构酸。

    Digital signature collection and authentication
    30.
    发明授权
    Digital signature collection and authentication 有权

    公开(公告)号：US08547363B2

    公开(公告)日：2013-10-01

    申请号：US12978031

    申请日：2010-12-23

    Applicant: Jianping Xu

    Inventor： Jianping Xu

    IPC: G06F3/033

    CPC classification number: G06K9/00167 ,  G06F3/0346 ,  G06F3/03545 ,  G06F3/043 ,  G06K9/00154 ,  G07C9/0015

    Abstract: A digital signature collection and authentication system includes an ink pen having an ultrasonic transmitter that transmits ultrasonic energy to a plurality of ultrasonic receivers. A computer triangulates the location of the pen versus time to generate the signature shape, and to generate velocity and acceleration data. The pen also includes a pressure sensitive tip to record pressure applied to the pen tip. The pen also includes a higher frequency burst transmitter useful to generate a time reference, and to transmit the pressure information. The computer packetizes the shape, velocity, acceleration, and pressure data with a time stamp and an IP address or phone number, encrypts the packet and sends it to a host computer for authentication.

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