公开(公告)号：US07339267B2

公开(公告)日：2008-03-04

申请号：US11140351

申请日：2005-05-26

Applicant: Vasile Romega Thompson ,  Jason Fender ,  Terry K. Daly ,  Jin-Wook Jang

Inventor： Vasile Romega Thompson ,  Jason Fender ,  Terry K. Daly ,  Jin-Wook Jang

IPC: H01L23/10

CPC classification number: H01L23/482 ,  H01L23/481 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/29111 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/10158 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15738 ,  H01L2924/15763 ,  H01L2924/01031 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/00

Abstract: Semiconductor packages (100) that prevent the leaching of gold from back metal layers (118) into the solder (164) and methods for fabricating the same are provided. An exemplary method comprises providing a semiconductor wafer stack (110) including metal pads (112) and a substrate (116). An adhesion/plating layer (115) is formed on the substrate (116). A layer of gold (118) is plated on the adhesion/plating layer (115). The layer of gold is etched in a street area (124) to expose edge portions (128) of the layer of gold (118) and the adhesion/plating layer (115). A layer of barrier metal (130) is deposited to form an edge seal (129) about the exposed edge portions (128). The edge seal (129) prevents the leaching of gold from back metal layers (118) into the solder (162) when the wafer stack (110) is soldered to a leadframe (162).

Abstract translation: 提供了防止金从后金属层（118）浸入焊料（164）中的半导体封装（100）及其制造方法。 一种示例性方法包括提供包括金属焊盘（112）和衬底（116）的半导体晶片堆叠（110）。 在基板（116）上形成粘合/镀层（115）。 一层金（118）被镀在粘合/镀层（115）上。 在街道区域（124）中蚀刻金层以暴露金层（118）和粘附/镀层（115）的边缘部分（128）。 沉积一层阻挡金属（130）以形成围绕暴露的边缘部分（128）的边缘密封（129）。 当晶片堆叠（110）被焊接到引线框架（162）时，边缘密封件（129）防止金从后金属层（118）浸入焊料（162）中。

公开(公告)号：US06790759B1

公开(公告)日：2004-09-14

申请号：US10631102

申请日：2003-07-31

Applicant: James Jen-Ho Wang ,  Jin-Wook Jang ,  Alfredo Mendoza ,  Rajashi Runton ,  Russell Shumway

Inventor： James Jen-Ho Wang ,  Jin-Wook Jang ,  Alfredo Mendoza ,  Rajashi Runton ,  Russell Shumway

IPC: H01L2144

CPC classification number: H01L24/16 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/081 ,  H01L2224/1147 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00012

Abstract: A semiconductor device (51) is provided. The device (51) comprises a die (53) having a contact pad (61) thereon, a redistribution conductor (59) having a base portion (64) which is in electrical communication with the contact pad (61) and a laterally extending portion (63), a bumped contact (65) which is in electrical communication with the redistribution conductor (59), and a passivation layer (57) disposed between the laterally extending portion (63) of the redistribution conductor (59) and the die (53). Preferably, the redistribution conductor (59) is convoluted and is adapted to peel or delaminate from the passivation layer (57) under sufficient stress so that it can shift relative to the passivation layer (57) and base portion (64) to relieve mechanical stress between substrate (69) and the die (53). Bump and coiled redistribution conductor (59) accommodating small CTE mis-match strain without failure allows DCA flip-chip to be reliable without underfill or additional assembly process.

Abstract translation: 提供半导体器件（51）。 所述装置（51）包括其上具有接触垫（61）的模具（53），具有与所述接触垫（61）电连通的基部（64）的再分配导体（59）和横向延伸部分 （63），与再分布导体（59）电连通的凸起触头（65）和设置在再分布导体（59）的横向延伸部分（63）和模具（...）之间的钝化层（57） 53）。 优选地，再分配导体（59）被卷积并且适于在足够的应力下从钝化层（57）剥离或分层，使得其可以相对于钝化层（57）和基部（64）移动以减轻机械应力 在基板（69）和模具（53）之间。 容纳小CTE失配应变而不会发生故障的凸起和卷绕再分配导体（59）允许DCA倒装芯片可靠，无需底部填充或额外的组装过程。