Abstract:
A method includes providing a silicon-containing die and providing a heat sink having a palladium layer over a first surface of the heat sink. A first gold layer is located over one of a first surface of the die or the palladium layer. The silicon-containing die is bonded to the heat sink, where bonding includes joining the silicon-containing die and the heat sink such that the first gold layer and the palladium layer are between the first surface of the silicon-containing die and the first surface of the heat sink, and heating the first gold layer and the palladium layer to form a die attach layer between the first surface of the silicon-containing die and the first surface of the heat sink, the die attach layer comprising a gold interface layer having a plurality of intermetallic precipitates, each of the plurality of intermetallic precipitates comprising palladium, gold, and silicon.
Abstract:
A random pitch impeller for a fuel pump has number of blades. An incremental angle of the blades is set by the expression: Δθ i = ( 360 N ) + ( - 1 ) i × Am × sin ( p 1 × 360 N × i ) cos ( P 2 × 360 N × i ) , where ΔθI is the incremental angle between the blades, N is the total number of blades (N=2, 3, 5, 7, 11, 13, 17, . . . ), Am is the distribution magnitude of the inter-blade interval (equally divided angle) (0
Abstract:
A semiconductor device (51) is provided. The device (51) comprises a die (53) having a contact pad (61) thereon, a redistribution conductor (59) having a base portion (64) which is in electrical communication with the contact pad (61) and a laterally extending portion (63), a bumped contact (65) which is in electrical communication with the redistribution conductor (59), and a passivation layer (57) disposed between the laterally extending portion (63) of the redistribution conductor (59) and the die (53). Preferably, the redistribution conductor (59) is convoluted and is adapted to peel or delaminate from the passivation layer (57) under sufficient stress so that it can shift relative to the passivation layer (57) and base portion (64) to relieve mechanical stress between substrate (69) and the die (53). Bump and coiled redistribution conductor (59) accommodating small CTE mis-match strain without failure allows DCA flip-chip to be reliable without underfill or additional assembly process.
Abstract:
The application discloses Factor VIII polypeptides comprising internal deletions of amino acids within the area of residues 741 to 1689, wherein the thrombin cleavage sites at about 741 and about 1689 are present, and a site at about 1648 is not present, as compared to human Factor VIII.
Abstract:
The present invention relates to a pharmaceutical vaccine composition comprising: (a) a pathogen-derived antigen selected from the group consisting of Mycobacterium tuberculosis antigen, Bacillus anthracis antigen, HAV (hepatitis A virus) antigen, HBV (hepatitis B virus) antigen, HCV (hepatitis C virus) antigen, HIV (human immunodeficiency virus) antigen, influenza virus antigen, HSV (herpes simplex virus) antigen, Hib (Haemophilus influenzae type b) antigen, Neisseria meningitidis antigen, Corynebacterium diphtheriae antigen, Bordetella pertussis antigen, Clostridium tetani antigen and Varicella virus antigen; (b) a deacylated non-toxic LOS (lipooligosaccharide); and (c) a pharmaceutically acceptable carrier.
Abstract:
A method and device are disclosed in which a a lead-free or low-lead die attach material is applied to a surface. An electronic die is positioned on the die attach material. An oxide of at least a specified thickness is formed over an exposed portion of the die attach material. Wire bonds are formed between the electronic die and the surface, and an encapsulant material is applied over the surface, the oxide, and the electronic die.
Abstract:
Semiconductor packages (100) that prevent the leaching of gold from back metal layers (118) into the solder (164) during the die attachment process and methods for fabricating the same are provided. A method in accordance with the invention comprises providing a semiconductor wafer stack (110) including a plurality of metal pads (112). An adhesion/plating layer (115) is formed on a surface (119) of a substrate (116). A layer of gold (118) is plated on a surface of the adhesion/plating layer (115). The layer of gold is etched in a street area (124) using standard photolithography techniques to expose edge portions (128) of the layer of gold (118) and the adhesion/plating layer (115). A layer of barrier metal (130) is deposited to form an edge seal (129) about the exposed edges (128) of the layer of gold (118) the adhesion/plating layer (115). The semiconductor wafer stack (110) is diced in the street area (124) and soldered to a leadframe (162) to form a semiconductor package (100) that provides for an edge seal (128) to prevent the leaching of gold from back metal layers (118) into the solder (162).
Abstract:
A semiconductor device (51) is provided. The device (51) comprises a die (53) having a contact pad (61) thereon, a redistribution conductor (59) having a base portion (64) which is in electrical communication with the contact pad (61) and a laterally extending portion (63), a bumped contact (65) which is in electrical communication with the redistribution conductor (59), and a passivation layer (57) disposed between the laterally extending portion (63) of the redistribution conductor (59) and the die (53). Preferably, the redistribution conductor (59) is convoluted and is adapted to peel or delaminate from the passivation layer (57) under sufficient stress so that it can shift relative to the passivation layer (57) and base portion (64) to relieve mechanical stress between substrate (69) and the die (53). Bump and coiled redistribution conductor (59) accommodating small CTE mis-match strain without failure allows DCA flip-chip to be reliable without underfill or additional assembly process.
Abstract:
A semiconductor package includes a wiring substrate including a plurality of solder pads; a chip including a plurality of chip pads connected to the solder pads through a plurality of solders; a sealing layer configured to seal the chip and the solders, at least one void being between the solders; and a solder extrusion prevention layer on one sidewall of the solder exposed by the at least one void.