公开(公告)号：US20080205113A1

公开(公告)日：2008-08-28

申请号：US12071745

申请日：2008-02-26

Applicant: UK-song Kang ,  Jung-bae Lee

Inventor： UK-song Kang ,  Jung-bae Lee

IPC: G11C5/06

CPC classification number: G11C5/025 ,  G11C5/04

Abstract: A multi memory chip stacked on a multi core CPU includes a plurality of memories, each memory corresponding to a CPU core from among the CPU cores and being configured to directly transmit data between the other memories of the multi memory chip.

Abstract translation: 堆叠在多核CPU上的多存储器芯片包括多个存储器，每个存储器对应于CPU核心中的CPU核心，并且被配置为直接在多存储器芯片的其他存储器之间传输数据。

公开(公告)号：US20080195922A1

公开(公告)日：2008-08-14

申请号：US11779345

申请日：2007-07-18

Applicant: Jung-Bae LEE

Inventor： Jung-Bae LEE

IPC: G06F11/10

CPC classification number: G06F11/1008

Abstract: A memory system including a memory controller and a memory and a related method are disclosed. The method includes communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory, decoding the command and executing an EDC operation related to the EDC data in parallel, and if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else immediately executing an operation indicated by the command without regard to completion of the EDC operation.

公开(公告)号：US20080195914A1

公开(公告)日：2008-08-14

申请号：US11862409

申请日：2007-09-27

Applicant: Jung-Bae LEE

Inventor： Jung-Bae LEE

IPC: H03M13/05

CPC classification number: G06F11/1008

Abstract: A memory system including a memory controller and a memory and a related method are disclosed. The method includes communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory, decoding the command and executing an EDC operation related to the EDC data in parallel, and if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else immediately executing an operation indicated by the command without regard to completion of the EDC operation.

Abstract translation: 公开了一种包括存储器控制器和存储器以及相关方法的存储器系统。 该方法包括将与命令相关联的命令和错误检测/校正（EDC）数据从存储器控制器传送到存储器，解码该命令并并行执行与EDC数据相关的EDC操作，并且如果命令是写入 命令，延迟执行由写入命令指示的写入操作，直到完成EDC操作，否则立即执行由命令指示的操作，而不考虑完成EDC操作。

公开(公告)号：US20080022179A1

公开(公告)日：2008-01-24

申请号：US11779977

申请日：2007-07-19

Applicant: Jung-Bae LEE

Inventor： Jung-Bae LEE

IPC: G06F11/08 ,  G08C25/02

CPC classification number: H04L1/1671 ,  H04L1/0025 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/0288 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03885

Abstract: A system having a transmission unit transmitting an output data signal formed from output data and related error detection code and a corresponding receiving unit. The output data signal is pre-emphasized by a pre-emphasis driver in the transmission unit. The receiving unit includes an equalizer equalizing the received output data signal and an error detector analyzing the error detection code to determine whether a bit error is present in the received data. Upon successive data transmission failures either an equalization coefficient in the equalizer or a pre-emphasis coefficient in the pre-emphasis driver are changed.

Abstract translation: 一种具有发送单元的系统，该发送单元发送由输出数据和相关错误检测码形成的输出数据信号和相应的接收单元。 输出数据信号由传输单元中的预加重驱动器预先强调。 接收单元包括均衡接收的输出数据信号的均衡器和分析错误检测码的误差检测器，以确定接收数据中是否存在位错误。 在连续数据传输故障时，均衡器中的均衡系数或预加重驱动器中的预加重系数被改变。

公开(公告)号：US20080013357A1

公开(公告)日：2008-01-17

申请号：US11863151

申请日：2007-09-27

Applicant: Chul-Woo PARK ,  Sung-Hoon KIM ,  Hyuk-Joon KWON ,  Jung-Bae LEE ,  Youn-Sik PARK

Inventor： Chul-Woo PARK ,  Sung-Hoon KIM ,  Hyuk-Joon KWON ,  Jung-Bae LEE ,  Youn-Sik PARK

IPC: G11C5/06

CPC classification number: H01L27/0207 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  H01L23/5226 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.

Abstract translation: 公开了一种半导体存储器件及其布置方法。 半导体存储器件包括在存储单元阵列上方沿相同方向布置在同一层上的列选择信号线和全局数据IO信号线; 在与列选择信号线垂直的方向上与位于存储单元阵列上方的列选择信号线布置在不同层上的字线和第一本地数据IO信号线; 以及在与第一本地数据IO信号线相同的方向上与列选择信号线和存储单元阵列上方的字线​​布置在不同层上的第二本地数据IO信号线。

公开(公告)号：US20070271424A1

公开(公告)日：2007-11-22

申请号：US11723821

申请日：2007-03-22

Applicant: Jung-Bae Lee ,  Hoe-Ju Chung

Inventor： Jung-Bae Lee ,  Hoe-Ju Chung

IPC: G06F12/00

CPC classification number: G06F13/1668

Abstract: A memory module, a memory system including a memory controller and a memory module and methods thereof. The example memory module may include a plurality of memory units each having an interface and at least one memory device. An example write operation method may include receiving a packet command at a given one of a plurality of memory units, each of the plurality of memory units including an interface and at least one memory device, extracting a command signal, an address and write data from the received packet command if the received packet command corresponds to a write operation, transferring the extracted write data to at least one memory device via write/read data lines internal to the given one memory unit and writing the transferred write data at the at least one memory device. An example read operation may include receiving a packet command at a given one of a plurality of memory units, each of the plurality of memory units including an interface and at least one memory device, extracting a command signal and an address from the received packet command if the received packet command corresponds to a read operation, transferring the extracted command signal and address to at least one memory device, receiving read data corresponding to the extracted command signal and address from the at least one memory device via write/read data lines internal to the given one memory unit and transmitting the received read data from the interface via read data lines external to the given one memory unit.

Abstract translation: 存储器模块，包括存储器控制器和存储器模块的存储器系统及其方法。 示例性存储器模块可以包括多个存储单元，每个存储器单元具有接口和至少一个存储器件。 示例性写入操作方法可以包括在多个存储器单元中的给定一个处接收分组命令，所述多个存储器单元中的每一个包括接口和至少一个存储器设备，提取命令信号，地址和写入数据 如果接收到的分组命令对应于写入操作，则接收到的分组命令，通过给定一个存储器单元内部的写入/读取数据线将提取的写入数据传送到至少一个存储器件，并将传送的写入数据写入至少一个 存储设备。 示例性读取操作可以包括在多个存储器单元中的给定一个处接收分组命令，所述多个存储器单元中的每一个包括接口和至少一个存储器设备，从接收到的分组命令中提取命令信号和地址 如果接收的分组命令对应于读取操作，则将所提取的命令信号和地址传送到至少一个存储器件，通过内部的写入/读取数据线从至少一个存储器件接收与所提取的命令信号和地址相对应的读取数据 到给定的一个存储器单元，并且通过给定的一个存储器单元外部的读取数据线从接口发送接收到的读取数据。

公开(公告)号：US20070250658A1

公开(公告)日：2007-10-25

申请号：US11745965

申请日：2007-05-08

Applicant: Jung-Bae LEE ,  Hoe-Ju CHUNG

Inventor： Jung-Bae LEE ,  Hoe-Ju CHUNG

IPC: G11C5/06

CPC classification number: G06F13/1673 ,  G06F13/1684

Abstract: The invention provides an improved memory system that addresses signal degradation due to transmission line effects. The improved memory system includes a first buffer, at least one first memory device coupled to the first buffer, and a plurality of signal traces. The first buffer and memory device are mounted on a motherboard. Likewise, the plurality of signal traces is routed on the motherboard. Doing so eliminates stub loads that cause signal reflection that, in turn, result in signal degradation.

Abstract translation: 本发明提供了一种改进的存储器系统，其解决了由于传输线效应引起的信号劣化。 改进的存储器系统包括第一缓冲器，耦合到第一缓冲器的至少一个第一存储器件和多个信号迹线。 第一个缓冲器和存储器件安装在主板上。 同样地，多个信号迹线在主板上路由。 这样做可以消除引起信号反射的短线负载，从而导致信号衰减。

公开(公告)号：US07236012B2

公开(公告)日：2007-06-26

申请号：US10970016

申请日：2004-10-22

Applicant: Geun-hee Cho ,  Jung-bae Lee

Inventor： Geun-hee Cho ,  Jung-bae Lee

IPC: H03K19/0175

CPC classification number: G11C7/1051 ,  G11C7/1057

Abstract: A data output driver of a semiconductor memory device can minimize a difference in slew rate of an output signal according to a selected bit organization. The data output driver includes a pull-up driver and a pull-down driver. The pull-up driver pulls up an output terminal and the pull-down driver pulls down the output terminal. In particular, current driving capabilities of the pull-up driver and/or the pull-down driver are changed in response to bit organization information signals of the semiconductor memory device.

Abstract translation: 半导体存储器件的数据输出驱动器可以根据所选位组织来最小化输出信号的转换速率差。 数据输出驱动器包括一个上拉驱动器和一个下拉驱动器。 上拉驱动器拉出输出端子，下拉驱动器拉出输出端子。 特别地，上拉驱动器和/或下拉驱动器的当前驱动能力响应于半导体存储器件的位组织信息信号而改变。

公开(公告)号：US07177214B2

公开(公告)日：2007-02-13

申请号：US10991729

申请日：2004-11-18

Applicant: Jung-Bae Lee

Inventor： Jung-Bae Lee

IPC: G11C7/00

CPC classification number: G11C8/08 ,  G11C7/12

Abstract: Methods for controlling the timing of a pre-charge operation in a memory device are provided. In embodiments of the present invention, the timing may be controlled by dynamically selecting a word line off time based on information about a number of column cycles. This may be accomplished, for example, by routing a word line disable signal via one of a first plurality of delay paths. The methods may further include dynamically selecting a bit line equalization start time based on the information about the number of column cycles. This may be accomplished, for example, by routing a bit line equalization start signal via one of a second plurality of delay paths. Pursuant to still further embodiments of the present invention, systems for controlling timing in a memory device are provided which include a control circuit that is configured to select a word line off time from a plurality of word line off times in response to a word line signal and information about a number of column cycles.

Abstract translation: 提供了用于控制存储器件中的预充电操作的定时的方法。 在本发明的实施例中，可以通过基于关于列周期数的信息来动态地选择字线关闭时间来控制定时。 这可以例如通过经由第一多个延迟路径中的一个来路由字线禁用信号来实现。 所述方法还可以包括基于关于列周期数的信息来动态地选择位线均衡开始时间。 这可以例如通过经由第二多个延迟路径之一路由位线均衡起始信号来实现。 根据本发明的另外的实施例，提供了一种用于控制存储器件中的定时的系统，其包括控制电路，其被配置为响应于字线信号从多个字线关闭时间选择字线关闭时间 以及关于多个列循环的信息。

公开(公告)号：US20050240718A1

公开(公告)日：2005-10-27

申请号：US11071586

申请日：2005-03-04

Applicant: Hoe-ju Chung ,  Jung-bae Lee

Inventor： Hoe-ju Chung ,  Jung-bae Lee

IPC: G11C7/10 ,  G06F12/00 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  G06F13/42

CPC classification number: G06F13/4243

Abstract: Provided is a memory system and a method that can initialize a data channel at a high speed without the need to increase the number of pins in a semiconductor memory device, and not requiring a circuit to perform an initialization. The memory system includes a memory module equipped with a plurality of semiconductor memory devices; a memory controller controlling the semiconductor memory devices; and a data channel and a command/address channel connected between the plurality of semiconductor memory devices and the memory controller, wherein read latencies and write latencies of the plurality of semiconductor memory devices are controlled by the memory controller.

Abstract translation: 提供了一种可以高速初始化数据信道的存储器系统和方法，而不需要增加半导体存储器件中的引脚数量，并且不需要电路来执行初始化。 存储器系统包括配备有多个半导体存储器件的存储器模块; 控制半导体存储器件的存储器控​​制器; 以及连接在所述多个半导体存储器件和所述存储器控制器之间的数据通道和命令/地址通道，其中所述多个半导体存储器件的读取延迟和写入延迟由所述存储器控制器控制。