公开(公告)号：US20070131930A1

公开(公告)日：2007-06-14

申请号：US11544611

申请日：2006-10-10

申请人： Kazuhiko Aida ,  Junji Hirase ,  Hisashi Ogawa ,  Chiaki Kudo

发明人： Kazuhiko Aida ,  Junji Hirase ,  Hisashi Ogawa ,  Chiaki Kudo

IPC分类号： H01L23/58

CPC分类号： H01L21/82345 ,  H01L21/823437 ,  H01L21/823443 ,  H01L27/0207 ,  H01L29/665

摘要： The following steps are carried out: forming a gate electrode on a semiconductor substrate with a gate insulating film interposed therebetween, forming a dummy gate electrode on the semiconductor substrate with a dummy gate insulating film interposed therebeweeen and forming another dummy gate electrode on the semiconductor substrate with an insulating film for isolation interposed therebetween; forming a metal film on the semiconductor while exposing the gate electrode and covering the dummy gate electrodes; and subjecting the semiconductor substrate to heat treatment and thus siliciding at least an upper part of the gate electrode. Since the gate electrode is silicided and the dummy gate electrodes are non-silicided, this restrains a short circuit from being caused between the gate electrode and adjacent one of the dummy gate electrodes.

摘要翻译： 执行以下步骤：在半导体衬底上形成栅极电极，并在其间插入栅极绝缘膜，在半导体衬底上形成虚拟栅极电极，并在其上插入虚拟栅极绝缘膜，并在半导体衬底上形成另一个虚设栅电极 其间插入有用于隔离的绝缘膜; 在半导体上形成金属膜，同时露出栅电极并覆盖伪栅电极; 对半导体基板进行热处理，至少使栅电极的上部被硅化。 由于栅电极是硅化的，并且虚拟栅电极是非硅化的，所以这抑制了在栅电极和相邻的一个虚拟栅电极之间的短路。

公开(公告)号：US20070090395A1

公开(公告)日：2007-04-26

申请号：US11525011

申请日：2006-09-22

申请人： Akio Sebe ,  Naoki Kotani ,  Shinji Takeoka ,  Gen Okazaki ,  Junji Hirase ,  Kazuhiko Aida

发明人： Akio Sebe ,  Naoki Kotani ,  Shinji Takeoka ,  Gen Okazaki ,  Junji Hirase ,  Kazuhiko Aida

IPC分类号： H01L29/45

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A MIS transistor includes a gate electrode portion, insulating sidewalls formed on side surfaces of the gate electrode portion, source/drain regions and a stress film formed so as to cover the gate electrode portion and the source/drain regions. A height of an upper surface of the gate electrode portion is smaller than a height of an upper edge of each of the insulating sidewalls. A thickness of first part of the stress film located on the gate electrode portion is larger than a thickness of second part of the stress film located on the source/drain regions.

摘要翻译： MIS晶体管包括栅电极部分，形成在栅电极部分的侧表面上的绝缘侧壁，源极/漏极区域和形成为覆盖栅电极部分和源极/漏极区域的应力膜。 栅电极部分的上表面的高度小于每个绝缘侧壁的上边缘的高度。 位于栅电极部分的应力膜的第一部分的厚度大于位于源/漏区上的应力膜的第二部分的厚度。

公开(公告)号：US20070069312A1

公开(公告)日：2007-03-29

申请号：US11491266

申请日：2006-07-24

申请人： Yoshihiro Satou ,  Junji Hirase

发明人： Yoshihiro Satou ,  Junji Hirase

IPC分类号： H01L29/94

CPC分类号： H01L21/823475 ,  H01L21/28097 ,  H01L21/28114 ,  H01L21/28518 ,  H01L21/823443 ,  H01L23/485 ,  H01L29/42376 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region formed in the semiconductor substrate and surrounded by the isolation region; a fully-silicided gate line formed on the isolation region and the active region; and an insulating sidewall continuously covering a side face of the gate line. At least a portion of the gate line has a projection projecting from the sidewall.

摘要翻译： 半导体器件包括：形成在半导体衬底中的隔离区; 形成在半导体衬底中并被隔离区包围的有源区; 形成在所述隔离区域和所述有源区域上的全硅化栅极线; 以及连续地覆盖栅极线的侧面的绝缘侧壁。 栅极线的至少一部分具有从侧壁突出的突起。

公开(公告)号：US07037733B2

公开(公告)日：2006-05-02

申请号：US10343762

申请日：2002-07-01

申请人： Satoshi Shibata ,  Junji Hirase ,  Tatsuo Sugiyama ,  Emi Kanasaki ,  Fumitoshi Kawase ,  Yasushi Naito

发明人： Satoshi Shibata ,  Junji Hirase ,  Tatsuo Sugiyama ,  Emi Kanasaki ,  Fumitoshi Kawase ,  Yasushi Naito

IPC分类号： H01L21/66 ,  G01N25/00 ,  G01J5/00

CPC分类号： G01J5/0003

摘要： When the emissivity ε on the reverse face of a substrate 10 is measured during annealing processing for the substrate 10, films made from a material that varies the emissivity ε, such as a first DPS film 15 used for forming a plug 15A, a second DPS film 17 used for forming a capacitor lower electrode 17A and a third DPS film 20 used for forming a capacitor upper electrode 20A, are formed on the top face of the substrate 10. On the other hand, no film made from a material that varies the emissivity ε, such as a DPS film, is formed on the reverse face of the substrate 10.

摘要翻译： 当在衬底10的退火处理期间测量衬底10的反面上的发射率ε时，由用于形成插头15A的第一DPS膜15，例如用于形成插头15A的第一DPS膜15的材料制成的膜，第二 用于形成用于形成电容器上电极20A的电容器下电极17A和第三DPS膜20的DPS膜17形成在基板10的顶面上。另一方面，没有由材料制成的膜 在基板10的背面上形成改变发射率ε（例如DPS膜）。

公开(公告)号：US5641699A

公开(公告)日：1997-06-24

申请号：US502557

申请日：1995-07-14

申请人： Junji Hirase ,  Shin Hashimoto

发明人： Junji Hirase ,  Shin Hashimoto

IPC分类号： H01L27/105 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/108 ,  H01L27/105

摘要： In a semiconductor device, an outer peripheral part of an integrated circuit region separated by an insulation part is defined as a dummy cell region and a center part except the outer peripheral part of the integrated circuit region is defined as an active cell region. Memory cells such as DRAM, SRAM, EEPROM, mask ROM are formed in the active cell region. In the integrated circuit region, plural cell forming regions are provided which are respectively defined by an isolation. Active cells each having a field effect semiconductor element are provided in a region included in the active cell region of each cell forming region. Dummy cells each having an element inoperable as an semiconductor element are provided in a region included in the dummy cell region of each cell forming region. At last one of dummy cells is made to be a P-N lacking dummy cell having a semiconductor element in construction including at least a gate and excluding at least one of P-N junction parts from the same construction as the field effect semiconductor element in the active cells. All dummy cells may be the P-N lacking dummy cells. Thereby, insulation defects through the P-N lacking dummy cell due to disturbance of gate pattern and the like in the dummy cell region is prevented.

摘要翻译： 在半导体器件中，由绝缘部分隔开的集成电路区域的外周部分被定义为虚设单元区域，并且除了集成电路区域的外周部分之外的中心部分被定义为有源单元区域。 诸如DRAM，SRAM，EEPROM，掩模ROM的存储单元形成在活动单元区域中。 在集成电路区域中，设置多个单元形成区，分别由隔离限定。 每个具有场效应半导体元件的有源电池被提供在每个电池形成区域的有源电池区域中包括的区域中。 每个具有不可用作半导体元件的元件的虚拟单元设置在每个单元形成区域的虚拟单元区域中包括的区域中。 最后一个虚设单元被制成为具有至少具有栅极并且从与活性单元中的场效应半导体元件相同结构的P-N结部分中的至少一个排列的至少一个半导体元件的P-N缺乏的虚设单元。 所有虚拟细胞可能是缺乏伪细胞的P-N。 因此，防止了由于虚设单元区域中的栅极图案等的干扰而导致的缺乏虚设单元的P-N的绝缘缺陷。

公开(公告)号：US20120056270A1

公开(公告)日：2012-03-08

申请号：US13294727

申请日：2011-11-11

申请人： Tomohiro FUJITA ,  Junji HIRASE ,  Yoshihiro SATO

发明人： Tomohiro FUJITA ,  Junji HIRASE ,  Yoshihiro SATO

IPC分类号： H01L27/092

CPC分类号： H01L29/4983 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/513 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/7833

摘要： A semiconductor device includes an NMIS transistor including a first gate insulating film containing a high-k dielectric and a first gate electrode provided on the first gate insulating film and containing a metal material and a PMIS transistor including a second gate insulating film containing a high-k dielectric and a second gate electrode provided on the second gate insulating film and containing a metal material. A side surface of the first gate insulating film is located at an inner side of a side surface of the first gate electrode. A ratio of a length of the first gate insulating film along a gate length direction to a length of the first gate electrode along the gate length direction is lower than a ratio of a length of the second gate insulating film along the gate length direction to a length of the second gate electrode along the gate length direction.

摘要翻译： 半导体器件包括NMIS晶体管，其包括含有高k电介质的第一栅极绝缘膜和设置在第一栅极绝缘膜上并且包含金属材料的第一栅电极和包含含有高k电介质的第二栅极绝缘膜的PMIS晶体管， k电介质和设置在所述第二栅极绝缘膜上并且包含金属材料的第二栅电极。 第一栅极绝缘膜的侧面位于第一栅电极的侧面的内侧。 第一栅极绝缘膜沿着栅极长度方向的长度与栅极长度方向上的第一栅电极的长度的比率小于栅极长度方向上的第二栅极绝缘膜的长度与栅极长度方向的长度的比 沿栅极长度方向的第二栅电极的长度。

公开(公告)号：US08129794B2

公开(公告)日：2012-03-06

申请号：US12357869

申请日：2009-01-22

申请人： Junji Hirase

发明人： Junji Hirase

IPC分类号： H01L21/336

CPC分类号： H01L21/82345 ,  H01L21/26513 ,  H01L29/105 ,  H01L29/517 ,  Y10S257/901

摘要： A semiconductor device includes a first MIS transistor, and a second MIS transistor having a threshold voltage higher than that of the first MIS transistor. The first MIS transistor includes a first gate insulating film made of a high-k insulating film formed on a first channel region, and a first gate electrode having a first conductive portion provided on and contacting the first gate insulating film and a second conductive portion. The second MIS transistor includes a second gate insulating film made of the high-k insulating film formed on a second channel region, and a second gate electrode having a third conductive portion provided on and contacting the second gate insulating film and a fourth conductive portion. The third conductive portion has a film thickness smaller than that of the first conductive portion, and is made of the same composition material as that of the first conductive portion.

摘要翻译： 半导体器件包括第一MIS晶体管和具有高于第一MIS晶体管的阈值电压的阈值电压的第二MIS晶体管。 第一MIS晶体管包括由形成在第一沟道区上的高k绝缘膜制成的第一栅极绝缘膜和具有设置在第一栅极绝缘膜上并与第一栅极绝缘膜接触的第一导电部分的第一栅电极和第二导电部分。 第二MIS晶体管包括由形成在第二沟道区上的高k绝缘膜制成的第二栅极绝缘膜和具有设置在第二栅极绝缘膜上并与第二栅极绝缘膜接触的第三导电部分的第二栅电极和第四导电部分。 第三导电部分的膜厚度小于第一导电部分的厚度，并且由与第一导电部分相同的组成材料制成。

公开(公告)号：US07923764B2

公开(公告)日：2011-04-12

申请号：US12505799

申请日：2009-07-20

申请人： Junji Hirase ,  Akio Sebe ,  Naoki Kotani ,  Gen Okazaki ,  Kazuhiko Aida ,  Shinji Takeoka

发明人： Junji Hirase ,  Akio Sebe ,  Naoki Kotani ,  Gen Okazaki ,  Kazuhiko Aida ,  Shinji Takeoka

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/4983 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.

摘要翻译： 半导体器件包括：形成在衬底的有源区上的高介电常数栅极绝缘膜; 形成在高介电常数栅极绝缘膜上的栅电极; 以及形成在栅电极的每个侧表面上的绝缘侧壁。 高介电常数栅极绝缘膜连续地形成为从栅极下方延伸到绝缘侧壁下方。 位于绝缘侧壁下方的高介电常数栅极绝缘膜的至少一部分的厚度比位于栅电极下方的高介电常数栅极绝缘膜的厚度的厚度小。

公开(公告)号：US07804146B2

公开(公告)日：2010-09-28

申请号：US12028392

申请日：2008-02-08

申请人： Hiroshi Ohkawa ,  Junji Hirase ,  Hisashi Ogawa ,  Kenji Yoneda

发明人： Hiroshi Ohkawa ,  Junji Hirase ,  Hisashi Ogawa ,  Kenji Yoneda

IPC分类号： H01L29/76

CPC分类号： H01L21/823857 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/518

摘要： A semiconductor device includes an N-type MOS transistor and a P-type MOS transistor. The N-type MOS transistor has a first gate insulating film and a first gate electrode. The P-type MOS transistor has a second gate insulating film and a second gate electrode. The first gate insulating film and the second gate insulating film are made of silicon oxynitride, and the first gate insulating film and the second gate insulating film are different from each other in nitrogen concentration profile.

摘要翻译： 半导体器件包括N型MOS晶体管和P型MOS晶体管。 N型MOS晶体管具有第一栅极绝缘膜和第一栅极电极。 P型MOS晶体管具有第二栅极绝缘膜和第二栅极电极。 第一栅极绝缘膜和第二栅极绝缘膜由氮氧化硅制成，并且第一栅极绝缘膜和第二栅极绝缘膜在氮浓度分布中彼此不同。

公开(公告)号：US07646065B2

公开(公告)日：2010-01-12

申请号：US11542269

申请日：2006-10-04

申请人： Naoki Kotani ,  Gen Okazaki ,  Shinji Takeoka ,  Junji Hirase ,  Akio Sebe ,  Kazuhiko Aida

发明人： Naoki Kotani ,  Gen Okazaki ,  Shinji Takeoka ,  Junji Hirase ,  Akio Sebe ,  Kazuhiko Aida

IPC分类号： H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28097 ,  H01L21/28123 ,  H01L29/4975 ,  H01L29/66545

摘要： A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region in the semiconductor substrate; a gate insulating film formed on the active region; and a gate electrode formed across the boundary between the active region and the isolation region adjacent to the active region. The gate electrode includes a first portion which is located above the active region with the gate insulating film interposed therebetween and is entirely made of a silicide in a thickness direction and a second portion which is located above the isolation region and is made of a silicon region and the silicide region covering the silicon region.

摘要翻译： 半导体器件包括：形成在半导体衬底中的隔离区; 由半导体衬底中的隔离区围绕的有源区; 形成在有源区上的栅极绝缘膜; 以及形成在有源区域和邻近有源区域的隔离区域之间的边界上的栅电极。 栅电极包括位于有源区上方的第一部分，栅极绝缘膜插入其间，并且在厚度方向上完全由硅化物制成，而第二部分位于隔离区上方，并由硅区域 以及覆盖硅区域的硅化物区域。