公开(公告)号：US08400850B2

公开(公告)日：2013-03-19

申请号：US13041566

申请日：2011-03-07

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: G11C7/00

CPC classification number: G11C7/02 ,  G11C5/14 ,  G11C11/413

Abstract: A semiconductor storage device in accordance with the present invention includes a first SRAM cell that stores data, and a word line circuit that outputs a first control signal used to activate the first SRAM cell. The word line control circuit gradually raises the voltage level of the first control signal from a substrate potential to a first power supply potential in a first activation period, maintains the voltage level of the first control signal at the first power supply potential in a second activation period subsequent to the first activation period, and raises the voltage level of the first control signal from the first power supply potential to a second power supply potential in a third activation period subsequent to the second activation period.

Abstract translation: 根据本发明的半导体存储装置包括存储数据的第一SRAM单元和输出用于激活第一SRAM单元的第一控制信号的字线电路。 字线控制电路在第一激活期间逐渐地将第一控制信号的电压电平从衬底电位升高到第一电源电位，在第二激活期间将第一控制信号的电压电平维持在第一电源电位 并且在第二激活周期之后的第三激活周期中将第一控制信号的电压电平从第一电源电位升高到第二电源电位。

公开(公告)号：US20120314510A1

公开(公告)日：2012-12-13

申请号：US13471360

申请日：2012-05-14

Applicant: Hidetoshi IKEDA ,  Koichi TAKEDA

Inventor： Hidetoshi IKEDA ,  Koichi TAKEDA

IPC: G11C7/06 ,  G11C7/08

CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1048 ,  G11C11/419

Abstract: Provided is a semiconductor memory device including a plurality of memory cells arranged in a matrix, a plurality of word lines arranged corresponding to each row of the memory cells, a plurality of bit line pairs arranged corresponding to each column of the memory cells, a column selector that selects any of the plurality of bit line pairs based on a column selection signal and connects the selected bit line pair to a data line pair, a precharge circuit that precharges the data line pair, a sense amplifier that amplifies a potential difference of the data line pair, and a control circuit that controls current for driving the sense amplifier based on potentials of the data line pair after a lapse of a specified period from start of amplification of the potential difference of the precharged data line pair by the sense amplifier.

Abstract translation: 提供了一种半导体存储器件，其包括以矩阵形式布置的多个存储器单元，对应于存储器单元的每一行布置的多个字线，对应于存储器单元的每列布置的多个位线对，列 选择器，其基于列选择信号选择多个位线对中的任何一个，并将所选择的位线对连接到数据线对，预充电数据线对的预充电电路，放大电位差的读出放大器 数据线对以及控制电路，其控制电流，用于在由读出放大器从预充电数据线对的电位差的放大开始经过指定时段之后基于数据线对的电位驱动读出放大器。

公开(公告)号：US20120202330A1

公开(公告)日：2012-08-09

申请号：US13367884

申请日：2012-02-07

Applicant: Koichi TAKEDA ,  Kiyoshi TAKEUCHI

Inventor： Koichi TAKEDA ,  Kiyoshi TAKEUCHI

IPC: H01L21/336

CPC classification number: H01L21/845 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1211 ,  Y10S257/903

Abstract: The present invention provides a semiconductor device including SRAM cell units each including a data holding section made up of a pair of driving transistors and a pair of load transistors, a data write section made up of a pair of access transistors, and a data read section made up of an access transistor and a driving transistor, wherein each of the transistors includes a semiconductor layer projecting upward from a base plane, a gate electrode extending from a top to opposite side surfaces of the semiconductor layer so as to stride the semiconductor layer, a gate insulating film between the gate electrode and the semiconductor layer, and source/drain areas, a longitudinal direction of each of the semiconductor layers is provided along a first direction, and for all the corresponding transistors between the SRAM cell units adjacent to each other in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer along the first direction in the other transistor.

Abstract translation: 本发明提供了包括SRAM单元单元的半导体器件，每个SRAM单元包括由一对驱动晶体管和一对负载晶体管构成的数据保持部分，由一对存取晶体管构成的数据写入部分和数据读取部分 由存取晶体管和驱动晶体管构成，其中每个晶体管包括从基板向上突出的半导体层，从半导体层的顶部延伸到相对侧表面的栅电极，以跨越半导体层， 栅极电极和半导体层之间的栅极绝缘膜以及源极/漏极区域，沿着第一方向设置每个半导体层的纵向方向，并且对于彼此相邻的SRAM单元单元之间的所有对应的晶体管 在第一方向上，一个对应的晶体管中的半导体层位于半导体1a的中心线上 沿另一个晶体管的第一个方向。

公开(公告)号：US08170205B2

公开(公告)日：2012-05-01

申请号：US12331587

申请日：2008-12-10

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: H04K1/04 ,  H04N7/167 ,  H04L9/00 ,  G06F11/30

CPC classification number: G06F12/1408

Abstract: The control unit includes a CPU which generates an access signal for performing writing or reading on the external memory, encryption/decryption means which, when the access signal is used for writing, encrypts an address designated by the CPU to generate a write address and encrypts write data contained in the access signal to generate write encrypted data, and which, when the access signal is used for reading, encrypts an address designated by the CPU to generate a read address and decrypts the encrypted data read from the external memory to generate plaintext data, and external control means which writes the write encrypted data in a position designated by the write address generated by the encryption/decryption means and which reads the encrypted data from a position designated by the read address generated by the encryption/decryption means and supplies the same to the encryption/decryption means for its decryption.

Abstract translation: 控制单元包括生成用于在外部存储器上进行写入或读取的访问信号的CPU，加密/解密装置，当访问信号用于写入时，加密由CPU指定的地址以产生写入地址并加密 写入访问信号中包含的数据以产生写入加密数据，当访问信号用于读取时，加密由CPU指定的地址以生成读取地址并对从外部存储器读取的加密数据进行解密以产生明文 数据和外部控制装置，其将写入加密数据写入由加密/解密装置生成的写入地址指定的位置，并且从由加密/解密装置产生的读取地址指定的位置读取加密数据， 与加密/解密手段相同，用于其解密。

公开(公告)号：US08124976B2

公开(公告)日：2012-02-28

申请号：US12095663

申请日：2006-12-01

Applicant: Koichi Takeda ,  Kiyoshi Takeuchi

Inventor： Koichi Takeda ,  Kiyoshi Takeuchi

IPC: H01L27/11

CPC classification number: H01L21/845 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1211 ,  Y10S257/903

Abstract: The present invention provides a semiconductor device including SRAM cell units each including a data holding section made up of a pair of driving transistors and a pair of load transistors, a data write section made up of a pair of access transistors, and a data read section made up of an access transistor and a driving transistor, wherein each of the transistors includes a semiconductor layer projecting upward from a base plane, a gate electrode extending from a top to opposite side surfaces of the semiconductor layer so as to stride the semiconductor layer, a gate insulating film between the gate electrode and the semiconductor layer, and source/drain areas, a longitudinal direction of each of the semiconductor layers is provided along a first direction, and for all the corresponding transistors between the SRAM cell units adjacent to each other in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer along the first direction in the other transistor.

Abstract translation: 本发明提供了包括SRAM单元单元的半导体器件，每个SRAM单元包括由一对驱动晶体管和一对负载晶体管构成的数据保持部分，由一对存取晶体管构成的数据写入部分和数据读取部分 由存取晶体管和驱动晶体管构成，其中每个晶体管包括从基板向上突出的半导体层，从半导体层的顶部延伸到相对侧表面的栅电极，以跨越半导体层， 栅极电极和半导体层之间的栅极绝缘膜以及源极/漏极区域，沿着第一方向设置每个半导体层的纵向方向，并且对于彼此相邻的SRAM单元单元之间的所有对应的晶体管 在第一方向上，一个对应的晶体管中的半导体层位于半导体1a的中心线上 沿另一个晶体管的第一个方向。

公开(公告)号：US20110222360A1

公开(公告)日：2011-09-15

申请号：US13041566

申请日：2011-03-07

Applicant: Koichi TAKEDA

Inventor： Koichi TAKEDA

IPC: G11C7/00

CPC classification number: G11C7/02 ,  G11C5/14 ,  G11C11/413

Abstract: A semiconductor storage device in accordance with the present invention includes a first SRAM cell that stores data, and a word line circuit that outputs a first control signal used to activate the first SRAM cell. The word line control circuit gradually raises the voltage level of the first control signal from a substrate potential to a first power supply potential in a first activation period, maintains the voltage level of the first control signal at the first power supply potential in a second activation period subsequent to the first activation period, and raises the voltage level of the first control signal from the first power supply potential to a second power supply potential in a third activation period subsequent to the second activation period.

Abstract translation: 根据本发明的半导体存储装置包括存储数据的第一SRAM单元和输出用于激活第一SRAM单元的第一控制信号的字线电路。 字线控制电路在第一激活期间逐渐地将第一控制信号的电压电平从衬底电位升高到第一电源电位，在第二激活期间将第一控制信号的电压电平维持在第一电源电位 并且在第二激活周期之后的第三激活周期中将第一控制信号的电压电平从第一电源电位升高到第二电源电位。

公开(公告)号：US07719043B2

公开(公告)日：2010-05-18

申请号：US11632352

申请日：2005-07-04

Applicant: Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Risho Koh ,  Kiyoshi Takeuchi ,  Masahiro Nomura ,  Koichi Takeda ,  Koichi Terashima ,  Masayasu Tanaka ,  Katsuhiko Tanaka

Inventor： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Risho Koh ,  Kiyoshi Takeuchi ,  Masahiro Nomura ,  Koichi Takeda ,  Koichi Terashima ,  Masayasu Tanaka ,  Katsuhiko Tanaka

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/7851

Abstract: The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a part of the semiconductor substrate, and an insulating film on the shallow substrate flat surface; and the protrusive semiconductor layer of the Fin type FET is formed of a portion protruding from the insulating film of the semiconductor raised portion.

Abstract translation: 本发明涉及一种半导体器件，其包括具有从衬底平面突出的突出半导体层的鳍型场效应晶体管（FET），形成为跨越突出半导体层的栅极电极，栅极电极 所述突出半导体层以及设置在所述突出半导体层中的源极和漏极区域，其中所述半导体器件在半导体衬底上具有具有鳍型FET的元件形成区域，设置在所述半导体衬底上的沟槽，用于将所述元件形成区域 来自另一个元件形成区域，以及沟槽中的元件隔离绝缘膜; 元件形成区域具有通过挖掘到比沟槽的底表面浅的深度而比半导体衬底的上表面更深的深浅的衬底平坦表面，从衬底平坦表面突出并形成的半导体凸起部分 的半导体衬底，以及在浅衬底平面上的绝缘膜; 并且鳍式FET的突出半导体层由从半导体凸起部分的绝缘膜突出的部分形成。

公开(公告)号：US07701018B2

公开(公告)日：2010-04-20

申请号：US10593300

申请日：2005-03-22

Applicant: Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe ,  Koichi Terashima

Inventor： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe ,  Koichi Terashima

IPC: H01L27/088

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/6681 ,  H01L2029/7858

Abstract: A semiconductor device comprising a first semiconductor region and a second semiconductor region, (a) wherein a field effect transistor is comprised of the first semiconductor region comprising at least one semiconductor layer(s) protruding upward from a substrate, a gate electrode(s) formed via an insulating film such that the gate electrode(s) strides over the semiconductor layer(s) and source/drain regions provided in the semiconductor layer(s) on both sides of the gate electrode(s), whereby a channel region is formed in at least both sides of the semiconductor layer(s), (b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel to the channel current direction.

Abstract translation: 一种包括第一半导体区域和第二半导体区域的半导体器件，（a）其中场效应晶体管由包括从衬底向上突出的至少一个半导体层的第一半导体区域，栅电极， 通过绝缘膜形成，使得栅电极跨越设置在栅电极两侧的半导体层中的半导体层和源极/漏极区，由此沟道区是 形成在所述半导体层的至少两侧，（b），其中所述第二半导体区域包括从所述衬底向上突出的半导体层，并且至少相对于与沟道垂直的方向的两端处的所述第一半导体区域相对 电流方向和面对第一半导体区域的半导体层的侧表面平行于沟道电流方向。

公开(公告)号：US20100091590A1

公开(公告)日：2010-04-15

申请号：US12585495

申请日：2009-09-16

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: G11C7/00 ,  G11C7/02 ,  G11C11/00

CPC classification number: G11C7/02 ,  G11C11/417 ,  G11C11/419

Abstract: A semiconductor memory apparatus includes an SRAM circuit having first SRAM cells that store data and second SRAM cells that amplify a potential difference of the data and store the potential difference, a word line driver circuit that outputs a first control signal for selecting one of the first SRAM cells to be read/written the data and a second control signal for selecting one of the second SRAM cells to be read/written the potential difference, a sense amplifier circuit that amplifies a potential difference of a read signal output from a bit line pair of the second SRAM cell selected according to the second control signal, and a write driver circuit that outputs a write signal to the bit line pair of the second SRAM cell selected according to the second control signal, and the write signal has a potential difference between bit lines larger than the read signal.

Abstract translation: 半导体存储装置包括SRAM电路，其具有存储数据的第一SRAM单元和放大数据的电位差并存储电位差的第二SRAM单元;输出第一控制信号的字线驱动电路，用于选择第一 要读/写数据的SRAM单元和用于选择要读/写电位差的第二SRAM单元之一的第二控制信号，放大从位线对输出的读信号的电位差的读出放大器电路 根据第二控制信号选择的第二SRAM单元;以及写入驱动器电路，其将写入信号输出到根据第二控制信号选择的第二SRAM单元的位线对，并且写入信号之间具有电位差， 位线大于读取信号。

公开(公告)号：US20090222507A1

公开(公告)日：2009-09-03

申请号：US12394415

申请日：2009-02-27

Applicant: Akira Koseki ,  Koichi Takeda

Inventor： Akira Koseki ,  Koichi Takeda

IPC: G06F15/173

CPC classification number: G06Q10/00

Abstract: A personal service support method for assisting an inquiry about a user operation in a virtual world, a computer program product, and a system for the same. The method includes: storing a dialog between a user and an agent; connecting the dialog in a list structure with another dialog in the list structure to produce a created dialog in a branch tree structure; and recording the created dialog in the branch tree structure. The computer program product tangibly embodies instructions which when implemented causes a computer to execute the steps of the method. The system includes: a dialog storage unit which stores a dialog between a user and an agent; and a dialog creating unit which connects the dialog in the list structure with another dialog in the list structure to create a dialog in a branch tree structure.

Abstract translation: 一种用于协助关于虚拟世界中的用户操作的查询的个人服务支持方法，计算机程序产品及其系统。 该方法包括：存储用户和代理之间的对话; 将列表结构中的对话框与列表结构中的另一个对话框相连，以便在分支树结构中生成创建的对话框; 并在分支树结构中记录创建的对话框。 计算机程序产品有形地体现了在实现时使计算机执行该方法的步骤的指令。 该系统包括：存储用户和代理之间的对话的对话存储单元; 以及对话创建单元，其将列表结构中的对话与列表结构中的另一个对话连接以在分支树结构中创建对话。