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142 条记录 (耗时 0.016 秒)

    Apparatus and method for multi-bit programming
    21.
    发明申请
    Apparatus and method for multi-bit programming 审中-公开
    多位编程的装置和方法

    公开(公告)号：US20090046510A1

    公开(公告)日：2009-02-19

    申请号：US12007775

    申请日：2008-01-15

    申请人： Seung-Hwan Song ,  Jun Jin Kong ,  Sung Chung Park ,  Heeseok Eun ,  Dong Hyuk Chae ,  Kyoung Lae Cho

    发明人： Seung-Hwan Song ,  Jun Jin Kong ,  Sung Chung Park ,  Heeseok Eun ,  Dong Hyuk Chae ,  Kyoung Lae Cho

    IPC分类号： G11C7/10

    CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C2211/5641

    摘要： Multi-bit programming apparatuses and methods are provided. A multi-bit programming apparatus may include: a first programming unit that stores data corresponding to a number of first bits in at least one first memory cell that may be connected to at least one first bit line; and a second programming unit that stores data corresponding to a number of second bits in at least one second memory cell that may be connected to at least one second bit line. Through this, it may be possible to improve data reliability and increase a number of bits to be stored in the entire memory cell.

    摘要翻译： 提供了多位编程设备和方法。 一种多位编程设备可以包括：第一编程单元，其存储对应于可连接到至少一个第一位线的至少一个第一存储器单元中的多个第一位的数据; 以及第二编程单元，其将可能连接到至少一个第二位线的至少一个第二存储器单元中的与第二位数相对应的数据存储。 由此，可以提高数据可靠性并增加要存储在整个存储单元中的位数。

    Non-volatile memory device and method of operating the same
    22.
    发明申请
    Non-volatile memory device and method of operating the same 有权
    非易失性存储器件及其操作方法

    公开(公告)号：US20080316824A1

    公开(公告)日：2008-12-25

    申请号：US12071349

    申请日：2008-02-20

    申请人： Ju-hee Park ,  Jae-wong Hyun ,  Kyoung-lae Cho ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kee-won Kwon

    发明人： Ju-hee Park ,  Jae-wong Hyun ,  Kyoung-lae Cho ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kee-won Kwon

    IPC分类号： G11C16/06 ,  G11C16/04

    CPC分类号： G11C11/5642 ,  G11C2211/5641 ,  G11C2211/5646

    摘要： Provided are a semiconductor device having a block state confirmation cell that may store information indicating the number of data bits written to a plurality of memory cells, a method of reading memory data based on the number of the data bits written, and/or a memory programming method of storing the information indicating the number of the data bits written. The semiconductor device may include one or more memory blocks and a controller. Each of the memory blocks may include a plurality of memory cells each storing data, and a block state confirmation cell storing information indicating the number of data bits written to the memory cells. The controller may read the data bits from the memory blocks based on the number of data bits, which is indicated in the information in the block state confirmation cell.

    摘要翻译： 提供了具有块状态确认单元的半导体器件，其可以存储指示写入多个存储器单元的数据位数的信息，基于写入的数据位的数量读取存储器数据的方法和/或存储器 存储指示写入数据位数的信息的编程方法。 半导体器件可以包括一个或多个存储器块和控制器。 每个存储器块可以包括存储数据的多个存储单元，以及存储指示写入存储单元的数据位数的信息的块状态确认单元。 控制器可以基于在块状态确认单元中的信息中指示的数据位数来从存储器块读取数据位。

    Method of writing/reading data into/from memory cell and page buffer using different codes for writing and reading operations
    23.
    发明申请
    Method of writing/reading data into/from memory cell and page buffer using different codes for writing and reading operations 有权
    使用不同的代码进行写入和读取操作，从存储单元和页面缓冲区写入/读取数据的方法

    公开(公告)号：US20080285352A1

    公开(公告)日：2008-11-20

    申请号：US12010481

    申请日：2008-01-25

    申请人： Kyoung-lae Cho ,  Yoon-dong Park ,  Jun-jin Kong ,  Seung-hoon Lee ,  Jae-woong Hyun ,  Sung-jae Byun ,  Ju-hee Park ,  Seung-hwan Song

    发明人： Kyoung-lae Cho ,  Yoon-dong Park ,  Jun-jin Kong ,  Seung-hoon Lee ,  Jae-woong Hyun ,  Sung-jae Byun ,  Ju-hee Park ,  Seung-hwan Song

    IPC分类号： G11C16/06

    CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5642

    摘要： Provided are a method of writing/reading data into/from a memory cell and a page buffer using different codes for the writing and reading operations. The method of writing/reading data into/from a memory cell that has a plurality of threshold voltage distributions includes a data writing operation and a data reading operation. In the data writing operation, data having a plurality of bits is written into the memory cell by using a plurality of writing codes corresponding to threshold voltage distributions. In the data reading operation, the data having a plurality of bits is read from the memory cell by using reading codes corresponding to the threshold voltage distributions from among the threshold voltage distributions. In the method of writing/reading data into/from a memory cell, a part of the writing codes is different from a corresponding part of the reading codes.

    摘要翻译： 提供了一种将数据写入/从存储单元读取数据的方法和使用不同代码进行写入和读取操作的页面缓冲器。 对具有多个阈值电压分布的存储单元写入/读取数据的方法包括数据写入操作和数据读取操作。 在数据写入操作中，通过使用与阈值电压分布对应的多个写入代码，将具有多个位的数据写入存储单元。 在数据读取操作中，通过使用与阈值电压分布中的阈值电压分布相对应的读取代码，从存储单元读取具有多个位的数据。 在将数据写入/从存储单元读取的方法中，写入代码的一部分与读取代码的相应部分不同。

    Memory cell programming method and semiconductor device for simultaneously programming a plurality of memory block groups
    24.
    发明申请
    Memory cell programming method and semiconductor device for simultaneously programming a plurality of memory block groups 有权
    用于同时编程多个存储块组的存储单元编程方法和半导体器件

    公开(公告)号：US20080285343A1

    公开(公告)日：2008-11-20

    申请号：US12081568

    申请日：2008-04-17

    申请人： Ju-hee Park ,  Jae-woong Hyun ,  Yoon-dong Park ,  Kyoung-lae Cho ,  Sung-jae Byun ,  Seung-hwan Song ,  Jun-jin Kong ,  Sung-chung Park

    发明人： Ju-hee Park ,  Jae-woong Hyun ,  Yoon-dong Park ,  Kyoung-lae Cho ,  Sung-jae Byun ,  Seung-hwan Song ,  Jun-jin Kong ,  Sung-chung Park

    IPC分类号： G11C16/04 ,  G11C8/00

    CPC分类号： H01L29/7883 ,  G11C16/10

    摘要： Provided are a memory cell programming method and a semiconductor device which may be capable of simultaneously writing a bit of data and then another bit of the data to a plurality of memory blocks. The memory programming method, in which M bits of data are written to a plurality of memory blocks, may include a data division operation and a data writing operation where M may be a natural number. In the data division operation, the plurality of memory blocks may be divided into a plurality of memory block groups. In the data writing operation, an ith bit of the data may be simultaneously written to two or more memory block groups from among the plurality memory block groups, and then an i+1th bit of the data may be simultaneously written to the two or more memory block groups from among the plurality memory block groups, where i is a natural number less than M.

    摘要翻译： 提供了一种存储器单元编程方法和半导体器件，其可以能够同时将数据位和数据的另一位写入多个存储块。 其中将M位数据写入多个存储块的存储器编程方法可以包括数据分割操作和数据写入操作，其中M可以是自然数。 在数据划分操作中，多个存储块可以被划分为多个存储块组。 在数据写入操作中，数据的第i / O位可以被同时写入到多个存储块组之中的两个或更多个存储块组，然后i + 1＆lt; / SUP>位可以从多个存储块组中的两个或更多个存储块组同时写入，其中i是小于M的自然数。

    Semiconductor memory devices including recess-type control gate electrodes and methods of fabricating the semiconductor memory devices
    26.
    发明申请
    Semiconductor memory devices including recess-type control gate electrodes and methods of fabricating the semiconductor memory devices 失效
    包括凹型控制栅电极的半导体存储器件和制造半导体存储器件的方法

    公开(公告)号：US20070272973A1

    公开(公告)日：2007-11-29

    申请号：US11709860

    申请日：2007-02-23

    申请人： Yoon-dong Park ,  June-mo Koo ,  Kyoung-lae Cho

    发明人： Yoon-dong Park ,  June-mo Koo ,  Kyoung-lae Cho

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7923

    摘要： A semiconductor memory device includes a semiconductor substrate, a control gate electrode recessed in the semiconductor substrate, a storage node layer interposed between a sidewall of the control gate electrode and the semiconductor substrate, a tunneling insulation layer interposed between the storage node layer and the semiconductor substrate, a blocking insulation layer interposed between the storage node layer and the control gate electrode, and first and second channel regions formed around a surface of the semiconductor substrate to at least partially surround the control gate electrode. The semiconductor memory device may include a plurality of control gate electrodes, storage node layers, tunneling insulation layers, blocking insulation layers, and continuous first and second channel regions. A method of fabricating the semiconductor memory device includes etching the semiconductor substrate to form a plurality of holes, forming the tunneling insulation layers, storage node layers, blocking insulation layers, and control gate electrodes.

    摘要翻译： 半导体存储器件包括半导体衬底，凹入半导体衬底中的控制栅极电极，插在控制栅电极的侧壁和半导体衬底之间的存储节点层，介于存储节点层和半导体衬底之间的隧道绝缘层 衬底，介于存储节点层和控制栅电极之间的阻挡绝缘层，以及形成在半导体衬底的表面周围以至少部分地围绕控制栅电极的第一和第二沟道区。 半导体存储器件可以包括多个控制栅电极，存储节点层，隧道绝缘层，阻挡绝缘层以及连续的第一和第二沟道区域。 制造半导体存储器件的方法包括蚀刻半导体衬底以形成多个孔，形成隧道绝缘层，存储节点层，阻挡绝缘层和控制栅电极。

    Method of operating memory controller, memory controller, memory device and memory system
    27.
    发明授权
    Method of operating memory controller, memory controller, memory device and memory system 有权
    操作内存控制器，内存控制器，内存设备和内存系统的方法

    公开(公告)号：US08830743B2

    公开(公告)日：2014-09-09

    申请号：US13445048

    申请日：2012-04-12

    申请人： Kyoung-Lae Cho ,  Jun-Jin Kong ,  Jae-Hong Kim

    发明人： Kyoung-Lae Cho ,  Jun-Jin Kong ,  Jae-Hong Kim

    IPC分类号： G11C16/04 ,  G11C29/56 ,  G11C11/56 ,  G11C16/34 ,  G11C29/12 ,  G11C29/44

    CPC分类号： G11C11/5642 ,  G11C16/3418 ,  G11C29/44 ,  G11C29/56008 ,  G11C2029/1208 ,  G11C2029/4402

    摘要： A method of operating a memory controller, a memory controller, a memory device and a memory system are provided. The method includes reading first data from a nonvolatile memory device using a first read voltage, the first data includes a uncorrectable error bit, reading second data from a nonvolatile memory device using a second read voltage different from the first read voltage, the second data includes an correctable error bit, and reprogramming the nonvolatile memory device according to the comparison result of the first read voltage and the second read voltage.

    摘要翻译： 提供了一种操作存储器控制器，存储器控制器，存储器件和存储器系统的方法。 该方法包括使用第一读取电压从非易失性存储器件读取第一数据，第一数据包括不可校正的误差位，使用不同于第一读取电压的第二读取电压从非易失性存储器件读取第二数据，第二数据包括 可校正错误位，并根据第一读取电压和第二读取电压的比较结果重新编程非易失性存储器件。